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/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/
H A DUQIcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DUHIcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DQIcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DHIcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DDFcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DSIcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DUSIcmp.c18 #define imm1 33 macro
35 {if (reg0 <= imm1) return 1; else return 0;}
67 {if (indreg0 <= imm1) return 1; else return 0;}
99 {if (imm0 <= imm1) return 1; else return 0;}
131 {if (limm0 <= imm1) return 1; else return 0;}
163 {if (adr0 <= imm1) return 1; else return 0;}
195 {if (adrreg0 <= imm1) return 1; else return 0;}
227 {if (adrx0 <= imm1) return 1; else return 0;}
259 {if (regx0 <= imm1) return 1; else return 0;}
H A DHIset.c14 #define imm1 33 macro
35 {reg0 = imm1; }
67 {indreg0 = imm1; }
99 {adr0 = imm1; }
131 {adrreg0 = imm1; }
163 {adrx0 = imm1; }
195 {regx0 = imm1; }
H A DSFset.c14 #define imm1 33 macro
35 {reg0 = imm1; }
67 {indreg0 = imm1; }
99 {adr0 = imm1; }
131 {adrreg0 = imm1; }
163 {adrx0 = imm1; }
195 {regx0 = imm1; }
H A DQIset.c14 #define imm1 33 macro
35 {reg0 = imm1; }
67 {indreg0 = imm1; }
99 {adr0 = imm1; }
131 {adrreg0 = imm1; }
163 {adrx0 = imm1; }
195 {regx0 = imm1; }
H A DSIset.c14 #define imm1 33 macro
35 {reg0 = imm1; }
67 {indreg0 = imm1; }
99 {adr0 = imm1; }
131 {adrreg0 = imm1; }
163 {adrx0 = imm1; }
195 {regx0 = imm1; }
H A Dgen_tst.c18 #define imm1 33 macro
/openbsd-src/gnu/llvm/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td139 def EXTUI : RRR_Inst<0x00, 0x04, 0x00, (outs AR:$r), (ins AR:$t, uimm5:$imm1, imm1_16:$imm2),
140 "extui\t$r, $t, $imm1, $imm2", []> {
141 bits<5> imm1;
144 let s = imm1{3-0};
145 let Inst{16} = imm1{4};
/openbsd-src/gnu/usr.bin/binutils-2.17/cpu/
H A Dm32r.cpu496 (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
671 (dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
1894 "rac $accd,$accs,$imm1"
1895 (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
1897 (set tmp1 (sll accs imm1))
1914 (emit rac-dsi accd (f-accs 0) (f-imm1 0))
1920 (emit rac-dsi accd accs (f-imm1 0))
1953 "rach $accd,$accs,$imm1"
1954 (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
1956 (set tmp1 (sll accs imm1))
[all …]
H A Dm32c.cpu366 (df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
2022 h-sint DFLT f-imm1-S
6524 ;<arith>.L:S #imm1,An -- for m32c
6527 (define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem)
6529 (dni (.sym op 32.l-s-imm1-S-an)
6530 (.str op ".l 32-imm1-S-an")
7061 ;<insn>.size #imm1,#imm2,dst -- for m32c
7063 (define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem)
7074 (define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 …
7076 …(insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr …
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SMEInstrInfo.td140 // MSR SVCRSM, #<imm1>
141 // MSR SVCRZA, #<imm1>
142 // MSR SVCRSMZA, #<imm1>
/openbsd-src/gnu/gcc/gcc/config/sparc/
H A Dsparc.c2886 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; in legitimate_address_p() local
2920 imm1 = rs2; in legitimate_address_p()
2951 imm1 = XEXP (rs1, 1); in legitimate_address_p()
2953 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1)) in legitimate_address_p()
2960 imm1 = XEXP (addr, 1); in legitimate_address_p()
2962 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1)) in legitimate_address_p()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td420 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
421 // in which imm = imm0 + imm1 and both imm0 and imm1 are simm12. We make imm0
422 // as large as possible and imm1 as small as possible so that we might be able
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DREADME-SSE.txt467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp232 unsigned Op0, uint64_t imm1, uint64_t imm2, in fastEmitInst_riir() argument
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td436 // PO T XO TX imm1 ].
461 // PO T XO IX TX imm1 ].
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td3179 ImmOpWithPattern imm1, ImmOpWithPattern imm2>
3180 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td4708 // SETPAN #imm1
H A DARMInstrInfo.td4867 // SETPAN #imm1
/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td1484 def imm1 : NVPTXInst<(outs regclass:$dst),

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