Home
last modified time | relevance | path

Searched refs:getVT (Results 1 – 25 of 45) sorted by relevance

12

/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DDAGISelMatcherEmitter.cpp666 << getEnumName(cast<EmitIntegerMatcher>(N)->getVT()) << ", "; in EmitMatcher()
675 << getEnumName(cast<EmitStringIntegerMatcher>(N)->getVT()) << ", " << Val in EmitMatcher()
686 OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", "; in EmitMatcher()
690 OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", "; in EmitMatcher()
793 OS << getEnumName(EN->getVT(i)) << ", "; in EmitMatcher()
H A DDAGISelMatcher.h825 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
849 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
874 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
1018 MVT::SimpleValueType getVT(unsigned i) const { in getVT() function
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DValueTypes.cpp563 MVT MVT::getVT(Type *Ty, bool HandleUnknown){ in getVT() function in MVT
586 getVT(VTy->getElementType(), /*HandleUnknown=*/ false), in getVT()
598 return MVT::getVT(Ty, HandleUnknown); in getEVT()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp209 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
H A DLoongArchISelLowering.cpp373 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLT(MVT::i32)) in lowerUINT_TO_FP()
398 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLE(MVT::i32)) in lowerSINT_TO_FP()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp628 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) { in tryShrinkShlLogicImm()
834 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in Select()
912 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) { in Select()
927 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32; in Select()
2134 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
H A DRISCVInstrInfo.td1190 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1194 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp562 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1152 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps()
3403 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3569 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3833 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
4020 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
4023 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
4129 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits(); in ComputeNumSignBits()
4136 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits(); in ComputeNumSignBits()
6304 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
6316 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
[all …]
H A DSelectionDAGDumper.cpp701 OS << ":" << N->getVT().getEVTString(); in print_details()
H A DSelectionDAGISel.cpp2629 if (cast<VTSDNode>(N)->getVT() == VT) in CheckValueType()
2633 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
H A DTargetLowering.cpp806 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyMultipleUseDemandedBits()
2163 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
2422 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
4501 !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), in SimplifySetCC()
4503 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); in SimplifySetCC()
4606 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
10211 EVT SatVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); in expandFP_TO_INT_SAT()
H A DLegalizeVectorOps.cpp1029 EVT OrigTy = cast<VTSDNode>(Node->getOperand(1))->getVT(); in ExpandSEXTINREG()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1521 : cast<VTSDNode>(N.getOperand(1))->getVT(); in DetectUseSxtw()
1590 if (T->getVT().getSizeInBits() == NumBits) { in keepsLowBits()
1663 return VN->getVT().getSizeInBits() <= 16; in isPositiveHalfWord()
H A DHexagonISelLowering.cpp1060 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSETCC()
2088 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2113 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp222 unsigned Width = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in LowerSIGN_EXTEND_INREG()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp873 MVT VT = MVT::getVT(ReadReg->getType()); in isReadRegisterSourceOfDivergence()
H A DSIISelLowering.cpp1041 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType()); in getTgtMemIntrinsic()
1072 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1085 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()); in getTgtMemIntrinsic()
1099 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1112 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1122 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT? in getTgtMemIntrinsic()
1139 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
10010 VTSign->getVT() == MVT::i8) || in performSignExtendInRegCombine()
10012 VTSign->getVT() == MVT::i16)) && in performSignExtendInRegCombine()
/openbsd-src/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h1509 static MVT getVT(Type *Ty, bool HandleUnknown = false);
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4014 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerVectorFP_TO_INT_SAT()
4086 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
6019 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerOperation()
8367 cast<VTSDNode>(Val.getOperand(1))->getVT().getFixedSizeInBits() - in lookThroughSignExtension()
13496 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
13507 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
13535 Info.memVT = MVT::getVT(I.getType()); in getTgtMemIntrinsic()
13546 Info.memVT = MVT::getVT(I.getOperand(0)->getType()); in getTgtMemIntrinsic()
13557 Info.memVT = MVT::getVT(Val->getType()); in getTgtMemIntrinsic()
15407 return TypeNode->getVT(); in calculatePreExtendType()
[all …]
H A DAArch64ISelDAGToDAG.cpp762 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
2190 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits(); in isBitfieldExtractOpFromSExtInReg()
5773 return cast<VTSDNode>(Root->getOperand(3))->getVT(); in getMemVTFromNode()
5775 return cast<VTSDNode>(Root->getOperand(4))->getVT(); in getMemVTFromNode()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp401 LLT OldLLT(MVT::getVT(CurArgInfo.Ty)); in lowerReturn()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp942 MVT VT = MVT::getVT(Outs[I].Ty); in checkReturn()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1855 cast<VTSDNode>(Op.getOperand(1).getNode())->getVT().getSimpleVT(); in LowerSIGN_EXTEND_INREG()
2319 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td966 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
967 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;

12