| /openbsd-src/gnu/llvm/llvm/lib/Target/BPF/ |
| H A D | BPFMIPeephole.cpp | 108 MachineInstr *DefInsn = MRI->getVRegDef(Reg); in isCopyFrom32Def() 123 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in isPhiFrom32Def() 160 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg()); in isMovFrom32Def() 195 MachineInstr *SllMI = MRI->getVRegDef(ShfReg); in eliminateZExtSeq() 209 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg()); in eliminateZExtSeq() 480 MI2 = MRI->getVRegDef(SrcReg); in eliminateTruncSeq() 490 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq() 497 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq() 523 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in eliminateTruncSeq()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 170 return MRI->getVRegDef(Reg); in getVRegDefOrNull() 178 MachineInstr *MI = MRI->getVRegDef(Reg); in getKnownLeadingZeroCount() 298 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs() 341 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs() 471 MachineInstr *RootPHI = MRI->getVRegDef(Src); in simplifyCode() 537 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() 554 MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1); in simplifyCode() 656 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() 666 MachineInstr *Splt = MRI->getVRegDef(ConvReg); in simplifyCode() 720 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() [all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 146 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() 157 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard() 165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() 171 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
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| H A D | A15SDOptimizer.cpp | 157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane() 250 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern() 251 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern() 302 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() 345 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies() 372 MachineInstr *NewMI = MRI->getVRegDef(Reg); in elideCopiesAndPHIs() 380 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopiesAndPHIs() 602 MachineInstr *Def = MRI->getVRegDef(I); in runOnInstruction()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 104 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY() 153 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents() 162 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents() 175 LoopStart = LookThroughCOPY(MRI->getVRegDef(StartReg), MRI); in findLoopComponents() 493 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop() 936 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs() 947 MachineInstr *Def = MRI->getVRegDef(GPR); in ReplaceConstByVPNOTs() 965 DeadInstructions.insert(MRI->getVRegDef(GPR)); in ReplaceConstByVPNOTs() 982 DeadInstructions.insert(MRI->getVRegDef(GPR)); in ReplaceConstByVPNOTs()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 442 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); in findInductionRegister() 450 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { in findInductionRegister() 469 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister() 505 IVOp = MRI->getVRegDef(F->first); in findInductionRegister() 608 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); in getLoopTripCount() 655 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount() 703 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount() 709 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount() 713 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount() 719 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount() [all …]
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| H A D | HexagonVExtract.cpp | 78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR); in genElemLoad() 149 MachineInstr *DefI = MRI.getVRegDef(VecR); in runOnMachineFunction() 183 MachineInstr *AlignaI = MRI.getVRegDef(AR); in runOnMachineFunction()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelector.cpp | 43 MachineInstr *RootI = MRI.getVRegDef(Root.getReg()); in isBaseWithConstantOffset() 48 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg()); in isBaseWithConstantOffset()
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| H A D | Utils.cpp | 95 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass() 319 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) && in getConstantVRegValWithLookThrough() 435 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal() 444 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() 454 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies() 638 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() 738 MachineInstr *Def = MRI.getVRegDef(LiveIn); in getFunctionLiveInPhysReg() 1054 if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element))) in getAnyConstantSplat() 1203 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg()); in isConstantOrConstantVector() 1338 DeadInstChain.insert(MRI.getVRegDef(Op.getReg())); in saveUsesAndErase()
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| H A D | CombinerHelper.cpp | 243 MachineInstr *Def = MRI.getVRegDef(Reg); in matchCombineConcatVectors() 721 GAnyLoad *LoadMI = dyn_cast<GAnyLoad>(MRI.getVRegDef(SrcReg)); in matchCombineLoadWithAndMask() 892 GLoad *LoadDef = cast<GLoad>(MRI.getVRegDef(LoadReg)); in applySextInRegOfLoad() 1367 MachineInstr *Add2Def = MRI.getVRegDef(Add2); in matchPtrAddImmedChain() 1778 MachineInstr *SrcInstr = MRI.getVRegDef(SrcReg); in matchCombineUnmergeConstant() 1826 return isa<GImplicitDef>(MRI.getVRegDef(SrcReg)); in matchCombineUnmergeUndef() 1894 MRI.getVRegDef(MI.getOperand(MI.getNumDefs()).getReg()); in applyCombineUnmergeZExtToZExt() 2160 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in matchCombineExtOfExt() 2238 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in matchCombineTruncOfExt() 2422 isConstantOrConstantSplatVector(*MRI.getVRegDef(SelMI.getCondReg()), MRI); in matchConstantSelectCmp() [all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 79 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd() 82 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd() 87 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd() 115 unsigned Opc = MRI.getVRegDef(R)->getOpcode(); in isSignExtended() 121 return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT; in isZeroExtended() 308 *MRI.getVRegDef(Store.getValueReg()), MRI); in matchSplitStoreZero128()
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| H A D | AArch64RegisterBankInfo.cpp | 529 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints() 704 auto ScalarDef = MRI.getVRegDef(ScalarReg); in getInstrMapping() 797 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 846 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 926 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 930 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() == in getInstrMapping()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 64 auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack() 77 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack() 106 MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg()); in foldConstantsIntoIntrinsics() 172 MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr; in propagateSPIRVType() 198 MachineInstr *Def = MRI.getVRegDef(Reg); in insertAssignInstr() 242 MachineInstr *Def = MRI.getVRegDef(Reg); in generateAssignInstrs() 271 MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in generateAssignInstrs() 372 unsigned Opcode = MRI.getVRegDef(SrcReg)->getOpcode(); in processInstrsWithTypeFolding()
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| H A D | SPIRVUtils.cpp | 216 MachineInstr *ConstInstr = MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant() 220 ConstInstr = MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant() 223 ConstInstr = MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 76 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt() 94 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt() 140 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt() 152 markDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt() 157 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt() 194 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineSExt() 208 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineSExt() 213 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineSExt() 241 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineTrunc() 324 markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts); in tryCombineTrunc() [all …]
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 400 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis() 451 MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis() 459 InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis() 473 if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1)) in generateExistingPhis() 477 MachineInstr *PhiInst = MRI.getVRegDef(LoopVal); in generateExistingPhis() 646 if (MachineInstr *InstOp2 = MRI.getVRegDef(PhiOp2)) in generatePhis() 814 MachineInstr *MI = MRI.getVRegDef(LCDef); in splitLifetimes() 944 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() 947 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() 1046 MachineInstr *Def = MRI.getVRegDef(reg); in updateInstruction() [all …]
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| H A D | MachineCycleAnalysis.cpp | 141 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!"); in isCycleInvariant() 145 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) in isCycleInvariant()
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| H A D | OptimizePHIs.cpp | 115 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle() 122 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
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| H A D | MachineLoopInfo.cpp | 197 assert(MRI->getVRegDef(Reg) && in isLoopInvariant() 202 if (contains(MRI->getVRegDef(Reg))) in isLoopInvariant()
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| H A D | MIRVRegNamerUtils.cpp | 81 return MRI.getVRegDef(MO.getReg())->getOpcode(); in getInstructionOpcodeHash() 143 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
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| H A D | LiveVariables.cpp | 129 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse() 164 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse() 175 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred); in HandleVirtRegUse() 587 MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(), in runOnBlock() 649 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in runOnMachineFunction() 799 const MachineInstr *Def = MRI.getVRegDef(Reg); in isLiveIn()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86FastPreTileConfig.cpp | 293 MachineInstr *MI = MRI->getVRegDef(TileReg); in getShape() 351 MachineInstr *TileDefMI = MRI->getVRegDef(InTileReg); in convertPHI() 377 MachineInstr *TileLoad = MRI->getVRegDef(InTileReg); in convertPHI() 464 DefMI = MRI->getVRegDef(InTileReg); in canonicalizePHIs() 605 MachineInstr *RowMI = MRI->getVRegDef(RowMO->getReg()); in configBasicBlock() 606 MachineInstr *ColMI = MRI->getVRegDef(ColMO->getReg()); in configBasicBlock()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFixBrTableDefaults.cpp | 61 auto ExtMI = MF.getRegInfo().getVRegDef(MI.getOperand(0).getReg()); in fixBrTableIndex() 127 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 185 MachineInstr &OffsetTail = *MRI->getVRegDef(Reg); in foldLargeOffset() 195 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); in foldLargeOffset() 257 MachineInstr &OffsetTail = *MRI->getVRegDef(Rs1); in foldShiftedOffset()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 468 MachineInstr *Def = MRI->getVRegDef(UseReg); in getRegSeqInit() 476 for (MachineInstr *SubDef = MRI->getVRegDef(Sub->getReg()); in getRegSeqInit() 479 SubDef = MRI->getVRegDef(Sub->getReg())) { in getRegSeqInit() 528 MachineInstr *Def = MRI->getVRegDef(UseReg); in tryToFoldACImm() 1010 MachineInstr *Def = MRI->getVRegDef(Op.getReg()); in getImmOrMaterializedImm() 1170 MachineInstr *SrcDef = MRI->getVRegDef(Src1); in tryFoldZeroHighBits() 1307 InstToErase = MRI->getVRegDef(SrcReg); in tryFoldFoldableCopy() 1371 MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg()); in tryFoldClamp() 1524 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod() 1570 const MachineInstr *SubDef = MRI->getVRegDef(Op->getReg()); in tryFoldRegSequence() [all …]
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