Home
last modified time | relevance | path

Searched refs:getTII (Results 1 – 12 of 12) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp262 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyFoldMergeToZext()
290 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyMutateAnyExtToZExt()
/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp44 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerReturn()
440 return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(), in lowerCall()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp186 FromMI.setDesc(Builder.getTII().get(ToOpcode)); in replaceOpcodeWith()
614 MI.setDesc(Builder.getTII().get(LoadOpc)); in applyCombineExtendingLoads()
1643 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
2518 if (Builder.getTII().produceSameValue(*I1, *I2, &MRI)) { in matchEqualDefs()
3077 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3080 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3129 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
3910 if (Builder.getTII().isExtendLikelyToBeFolded(*ExtMI, MRI)) in matchExtendThroughPhis()
4174 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
4811 MI.setDesc(Builder.getTII().get(NewOpc)); in matchMulOBy2()
[all …]
H A DMachineIRBuilder.cpp40 return BuildMI(getMF(), {getDL(), getPCSections()}, getTII().get(Opcode)); in buildInstrNoInsert()
58 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
71 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
H A DLegalizerHelper.cpp723 << MIRBuilder.getTII().getName(Opc) << "\n"); in createMemLibcall()
732 isLibCallInTailPosition(MI, MIRBuilder.getTII(), MRI); in createMemLibcall()
2598 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); in widenScalar()
3242 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); in changeOpcode()
3288 const auto &TII = MIRBuilder.getTII(); in lower()
5636 const auto &TII = MIRBuilder.getTII(); in lowerBitCount()
7590 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::COPY)); in lowerVectorReduction()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp475 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
H A DMipsCallLowering.cpp545 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DRDFGraph.h666 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h267 const TargetInstrInfo &getTII() { in getTII() function
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1950 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
3256 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, in loadInputValue()
4928 MI.setDesc(B.getTII().get(NewOpcode)); in legalizeImageIntrinsic()
5250 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD)); in legalizeSBufferLoad()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DRDFGraph.cpp225 OS << Print(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()