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Searched refs:getSubReg (Results 1 – 25 of 158) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI()
107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI()
150 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicRMW128()
151 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicRMW128()
153 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicRMW128()
154 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicRMW128()
227 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
228 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
230 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
231 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp513 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
865 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
868 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
911 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
948 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
953 if (MODef.getSubReg()) in getNextRewritableSource()
996 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1004 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
1073 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1083 return MODef.getSubReg() == 0; in getNextRewritableSource()
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H A DDetectDeadLanes.cpp156 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
195 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
291 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
340 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
392 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
406 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
421 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
454 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
H A DCalcSpillWeights.cpp52 Sub = MI->getOperand(0).getSubReg(); in copyHint()
54 HSub = MI->getOperand(1).getSubReg(); in copyHint()
56 Sub = MI->getOperand(1).getSubReg(); in copyHint()
58 HSub = MI->getOperand(0).getSubReg(); in copyHint()
68 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
H A DRegAllocFast.cpp867 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
869 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
900 if (MO.getSubReg() && !MO.isUndef()) { in defineLiveThroughVirtReg()
991 if (MI.isCopy() && MI.getOperand(1).getSubReg() == 0) { in useVirtReg()
1024 if (!MO.getSubReg()) { in setPhysReg()
1031 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1178 (MO.getSubReg() != 0 && !MO.isUndef())) in allocateInstruction()
1262 (MO0.getSubReg() == 0 && !MO0.isUndef()); in allocateInstruction()
1264 (MO1.getSubReg() == 0 && !MO1.isUndef()); in allocateInstruction()
1280 (MO.getSubReg() && !MO.isUndef())) { in allocateInstruction()
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H A DTargetInstrInfo.cpp186 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
187 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
188 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl()
451 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
537 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
583 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) { in foldMemoryOperand()
1066 if (DefReg.isVirtual() && MI.getOperand(0).getSubReg() && in isReallyTriviallyReMaterializableGeneric()
1421 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1447 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1472 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp140 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in __anona05bf9b30111::EliminateFrameIndex
141 return TRI.getSubReg(Reg, Idx); in getSubReg()
244 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); in processSTQ()
245 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in processSTQ()
265 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
266 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
375 Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd); in processSTVM512()
376 Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even); in processSTVM512()
421 Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd); in processLDVM512()
422 Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even); in processLDVM512()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp33 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
34 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
37 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
38 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
113 if (MO->getSubReg()) in getRegAllocationHints()
114 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
115 if (VRRegMO->getSubReg()) in getRegAllocationHints()
116 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp120 Register SrcSubReg = I.getOperand(1).getSubReg(); in processReg()
122 if (SrcSubReg != Def.getOperand(0).getSubReg()) in processReg()
134 I.getOperand(1).setSubReg(DefSrcMO.getSubReg()); in processReg()
155 switch (I.getOperand(0).getSubReg()) { in processReg()
H A DR600ExpandSpecialInstrs.cpp211 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
218 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIFoldOperands.cpp310 Old.substVirtReg(New->getReg(), New->getSubReg(), *TRI); in updateOperand()
478 !Sub->getSubReg() && TII->isFoldableCopy(*SubDef); in getRegSeqInit()
530 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
579 (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)) in foldOperand()
596 if (RSUse.getSubReg() != RegSeqDstSubReg) in foldOperand()
705 !UseMI->getOperand(1).getSubReg()) { in foldOperand()
710 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
850 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
871 if (TRI->hasVectorRegisters(RC) && OpToFold.getSubReg()) { in foldOperand()
872 unsigned SubReg = OpToFold.getSubReg(); in foldOperand()
[all …]
H A DSIFrameLowering.cpp174 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
175 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
246 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToMemory()
267 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToVGPRLane()
293 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromMemory()
312 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromVGPRLane()
414 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
415 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
453 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
454 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
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H A DSIOptimizeExecMaskingPreRA.cpp139 unsigned CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
143 CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
165 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
205 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg()); in optimizeVcndVcmpPair()
246 if (CC->getSubReg()) { in optimizeVcndVcmpPair()
247 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(CC->getSubReg()); in optimizeVcndVcmpPair()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp259 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
320 if (!Op.getSubReg()) in profit()
324 if (MI->getOperand(1).getSubReg() != 0) in profit()
443 if (Op.getSubReg()) in isProfitable()
602 unsigned SR = Op.getSubReg(); in createHalfInstr()
648 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
651 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
657 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
661 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
673 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
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H A DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonSplitConst32AndConst64.cpp87 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
88 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DHexagonAsmPrinter.cpp136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
465 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
466 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
542 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
543 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
554 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
555 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
568 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
569 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
H A DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy()
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy()
128 return S.getSubReg(); in run()
H A DHexagonExpandCondsets.cpp180 Sub(Op.getSubReg()) {} in RegisterRef()
326 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
378 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
613 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
668 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
669 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
673 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
695 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split()
906 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
908 PredOp.getSubReg()); in predicateAt()
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H A DHexagonInstrInfo.cpp136 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
137 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
922 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
923 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
1139 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1140 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1154 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1163 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1172 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1187 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp537 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
538 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
539 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
540 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
542 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
543 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
544 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
545 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
547 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
548 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
[all …]
/openbsd-src/gnu/llvm/llvm/tools/llvm-reduce/deltas/
H A DReduceRegisterDefs.cpp54 TargetInstrInfo::RegSubRegPair RegPair(MO.getReg(), MO.getSubReg()); in removeDefsFromFunction()
76 TargetInstrInfo::RegSubRegPair RegPair(MO.getReg(), MO.getSubReg()); in removeDefsFromFunction()
/openbsd-src/gnu/llvm/llvm/lib/MC/
H A DMCRegisterInfo.cpp27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo

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