Searched refs:getShiftValue (Results 1 – 11 of 11) sorted by relevance
283 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()600 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl()627 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue()
1201 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); in printAddSubImm()1231 AArch64_AM::getShiftValue(Val) == 0) in printShifter()1234 << " " << markup("<imm:") << "#" << AArch64_AM::getShiftValue(Val) in printShifter()2019 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) { in printImm8OptLsl()2027 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); in printImm8OptLsl()2029 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); in printImm8OptLsl()
86 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() function
175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare()
57 let FunctionMapper = "AArch64_AM::getShiftValue" in
1806 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 && in mergeUpdateInsn()1876 if (AArch64_AM::getShiftValue(MI.getOperand(3).getImm())) in isMatchingUpdateInsn()
1493 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0))); in emitInstruction()
889 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast()916 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast()924 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast()
2520 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg()2528 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg()
3532 unsigned Shift = AArch64_AM::getShiftValue(MI.getOperand(3).getImm()); in canMergeRegUpdate()
2458 OS << ", lsl #" << AArch64_AM::getShiftValue(Shift) << ">"; in print()