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Searched refs:getSUnit (Results 1 – 25 of 31) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DScheduleDAG.cpp112 if (!Required && PredDep.getSUnit() == D.getSUnit()) in addPred()
118 SUnit *PredSU = PredDep.getSUnit(); in addPred()
136 SUnit *N = D.getSUnit(); in addPred()
183 SUnit *N = D.getSUnit(); in removePred()
225 SUnit *SuccSU = SuccDep.getSUnit(); in setDepthDirty()
240 SUnit *PredSU = PredDep.getSUnit(); in setHeightDirty()
273 SUnit *PredSU = PredDep.getSUnit(); in ComputeDepth()
304 SUnit *SuccSU = SuccDep.getSUnit(); in ComputeHeight()
330 unsigned MaxDepth = BestI->getSUnit()->getDepth(); in biasCriticalPath()
333 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth) in biasCriticalPath()
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H A DMachinePipeliner.cpp646 NewInstrChanges[KV.first] = InstrChanges[getSUnit(KV.first)]; in schedule()
713 SUnit *SuccSU = SI.getSUnit(); in isSuccOrder()
881 SUnit *SU = getSUnit(UseMI); in updatePhiDependences()
901 SUnit *SU = getSUnit(DefMI); in updatePhiDependences()
922 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
956 SUnit *DefSU = getSUnit(DefMI); in changeDependences()
963 SUnit *LastSU = getSUnit(LastMI); in changeDependences()
973 if (P.getSUnit() == DefSU) in changeDependences()
976 Topo.RemovePred(&I, Deps[i].getSUnit()); in changeDependences()
982 if (P.getSUnit() == &I && P.getKind() == SDep::Order) in changeDependences()
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H A DMacroFusion.cpp41 return SI.getSUnit(); in getPredClusterSU()
83 if (SI.getSUnit() == &SecondSU) in fuseInstructionPair()
87 if (SI.getSUnit() == &FirstSU) in fuseInstructionPair()
100 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
113 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
182 SUnit &DepSU = *Dep.getSUnit(); in scheduleAdjacentImpl()
H A DVLIWMachineScheduler.cpp97 if (S.getSUnit() == SUu && S.getLatency() > 0) in hasDependence()
312 unsigned PredReadyCycle = PI.getSUnit()->TopReadyCycle; in releaseTopNode()
330 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; in releaseBottomNode()
554 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2)) in isSingleUnscheduledPred()
569 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2)) in isSingleUnscheduledSucc()
667 if (isSingleUnscheduledPred(SI.getSUnit(), SU)) in SchedulingCost()
673 if (isSingleUnscheduledSucc(PI.getSUnit(), SU)) in SchedulingCost()
711 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()
713 Top.ResourceModel->isInPacket(PI.getSUnit())) { in SchedulingCost()
720 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
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H A DLatencyPriorityQueue.cpp59 SUnit &Pred = *P.getSUnit(); in getSingleUnscheduledPred()
77 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
91 AdjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
H A DScheduleDAGInstrs.cpp1212 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU)) in addEdge()
1214 Topo.AddPredQueued(SuccSU, PredDep.getSUnit()); in addEdge()
1290 unsigned PredNum = PredDep.getSUnit()->NodeNum; in visitPostorderNode()
1318 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount; in visitPostorderEdge()
1324 ConnectionPairs.emplace_back(PredDep.getSUnit(), Succ); in visitCrossEdge()
1371 const SUnit *PredSU = PredDep.getSUnit(); in joinPredSubtree()
1447 !SuccDep.getSUnit()->isBoundaryNode()) in hasDataSucc()
1474 || PredDep.getSUnit()->isBoundaryNode()) { in compute()
1478 if (Impl.isVisited(PredDep.getSUnit())) { in compute()
1482 Impl.visitPreorder(PredDep.getSUnit()); in compute()
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H A DMachineScheduler.cpp645 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
682 SUnit *PredSU = PredEdge->getSUnit(); in releasePred()
936 if (SUnit *SU = getSUnit(&MI)) in dumpSchedule()
1357 const SUnit *DefSU = getSUnit(DefMI); in computeCyclicCriticalPath()
1655 if (Succ.getSUnit() == SUb) in clusterNeighboringMemOps()
1657 LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum in clusterNeighboringMemOps()
1659 DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial)); in clusterNeighboringMemOps()
1669 if (Pred.getSUnit() == SUa) in clusterNeighboringMemOps()
1671 LLVM_DEBUG(dbgs() << " Copy Pred SU(" << Pred.getSUnit()->NodeNum in clusterNeighboringMemOps()
1673 DAG->addEdge(SUa, SDep(Pred.getSUnit(), SDep::Artificial)); in clusterNeighboringMemOps()
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H A DAggressiveAntiDepBreaker.cpp276 const SUnit *PredSU = Pred.getSUnit(); in CriticalPathStep()
289 return (Next) ? Next->getSUnit() : nullptr; in CriticalPathStep()
832 SUnit *NextSU = Edge->getSUnit(); in BreakAntiDependencies()
875 if (Pred.getSUnit() == NextSU ? (Pred.getKind() != SDep::Anti || in BreakAntiDependencies()
884 if ((Pred.getSUnit() == NextSU) && (Pred.getKind() != SDep::Anti) && in BreakAntiDependencies()
889 } else if ((Pred.getSUnit() != NextSU) && in BreakAntiDependencies()
H A DCriticalAntiDepBreaker.cpp145 const SUnit *PredSU = P.getSUnit(); in CriticalPathStep()
562 const SUnit *NextSU = Edge->getSUnit(); in BreakAntiDependencies()
585 if (P.getSUnit() == NextSU in BreakAntiDependencies()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNMinRegStrategy.cpp90 for (auto PDep : SDep.getSUnit()->Preds) { in getReadySuccessors()
91 auto PSU = PDep.getSUnit(); in getReadySuccessors()
180 if (S.getSUnit()->isBoundaryNode() || isScheduled(S.getSUnit()) || in bumpPredsPriority()
183 for (const auto &P : S.getSUnit()->Preds) { in bumpPredsPriority()
184 auto PSU = P.getSUnit(); in bumpPredsPriority()
196 if (!P.getSUnit()->isBoundaryNode() && !isScheduled(P.getSUnit()) && in bumpPredsPriority()
197 Set.insert(P.getSUnit()).second) in bumpPredsPriority()
198 Worklist.push_back(P.getSUnit()); in bumpPredsPriority()
215 auto SuccSU = S.getSUnit(); in releaseSuccessors()
H A DAMDGPUExportClustering.cpp70 SUnit *PredSU = Pred.getSUnit(); in buildCluster()
86 SUnit *PredSU = Pred.getSUnit(); in removeExportDependencies()
95 SUnit *ExportPredSU = ExportPred.getSUnit(); in removeExportDependencies()
130 removeExportDependencies(DAG, *Succ.getSUnit()); in apply()
H A DSIMachineScheduler.cpp425 if (BC->isSUInBlock(Succ.getSUnit(), ID)) in undoSchedule()
435 SUnit *SuccSU = SuccEdge->getSUnit(); in undoReleaseSucc()
445 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
466 SUnit *SuccSU = Succ.getSUnit(); in releaseSuccessors()
499 NodeNum2Index.find(Succ.getSUnit()->NodeNum); in nodeScheduled()
647 if (PredDep.getSUnit() == &FromSU && in hasDataDependencyPred()
802 SUnit *Pred = PredDep.getSUnit(); in colorComputeReservedDependencies()
844 SUnit *Succ = SuccDep.getSUnit(); in colorComputeReservedDependencies()
926 SUnit *Succ = SuccDep.getSUnit(); in colorEndsAccordingToDependencies()
996 SUnit *Succ = SuccDep.getSUnit(); in colorMergeConstantLoadsNextGroup()
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H A DGCNILPSched.cpp66 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
110 unsigned Height = Succ.getSUnit()->getHeight(); in closestSucc()
277 auto PredSU = PredEdge.getSUnit(); in releasePredecessors()
H A DAMDGPUIGroupLP.cpp203 for (auto &SP : S.getSUnit()->Preds) in resetEdges()
204 if (SP.getSUnit() == &SU) in resetEdges()
205 S.getSUnit()->removePred(SP); in resetEdges()
430 Succ->Preds, [&Pred](SDep &P) { return P.getSUnit() == Pred; }); in removeEdges()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp150 S.getSUnit()->NumPredsLeft == 1) { in EmitInstruction()
151 UsesDotCur = S.getSUnit(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
167 PrefVectorStoreNew = S.getSUnit(); in EmitInstruction()
H A DHexagonSubtarget.cpp277 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
284 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
285 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
288 SI.getSUnit()->setDepthDirty(); in apply()
472 MachineInstr *DDst = DDep.getSUnit()->getInstr(); in adjustSchedDependency()
560 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()
608 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()
625 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
626 return I.getSUnit(); in getZeroLatency()
703 if (ExclSrc.count(I.getSUnit()) == 0 && in isBestZeroLatency()
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H A DHexagonVLIWPacketizer.cpp937 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti && in restrictingDepExistInPacket()
1005 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data && in arePredicatesComplements()
1413 if (SUJ->Succs[i].getSUnit() != SUI) in isLegalToPacketizeTogether()
1921 if (Pred.getSUnit() == SUJ) in calcStall()
1932 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1) in calcStall()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp226 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
234 Topo.AddPred(SU, D.getSUnit()); in AddPred()
242 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
402 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
567 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
569 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
824 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
846 assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && in UnscheduleNodeBottomUp()
902 LiveRegGens[Reg] = Succ.getSUnit(); in UnscheduleNodeBottomUp()
905 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) in UnscheduleNodeBottomUp()
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H A DResourcePriorityQueue.cpp73 SUnit *PredSU = Pred.getSUnit(); in numberRCValPredInSU()
111 SUnit *SuccSU = Succ.getSUnit(); in numberRCValSuccInSU()
212 SUnit &PredSU = *Pred.getSUnit(); in getSingleUnscheduledPred()
229 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
273 if (Succ.getSUnit() == SU) in isResourceAvailable()
498 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
500 --Pred.getSUnit()->NumRegDefsLeft; in scheduledNode()
513 adjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
H A DScheduleDAGFast.cpp136 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
167 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
190 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) { in ScheduleNodeBottomUp()
281 else if (Pred.getSUnit()->getNode() && in CopyAndMoveSuccessors()
282 Pred.getSUnit()->getNode()->isOperandOf(LoadNode)) in CopyAndMoveSuccessors()
294 if (ChainPred.getSUnit()) { in CopyAndMoveSuccessors()
313 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
321 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
358 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
394 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
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H A DScheduleDAGVLIW.cpp110 SUnit *SuccSU = D.getSUnit(); in releaseSucc()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
47 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isLoadAfterStore()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
73 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isBCTRAfterSet()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h152 SUnit *getSUnit() const;
433 if (Pred.getSUnit() == N) in isPred()
441 if (Succ.getSUnit() == N) in isSucc()
480 inline SUnit *SDep::getSUnit() const { return Dep.getPointer(); } in getSUnit() function
635 return Node->Preds[Operand].getSUnit();
H A DScheduleDAGInstrs.h287 SUnit *getSUnit(MachineInstr *MI) const;
391 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const { in getSUnit() function
H A DMachinePipeliner.h254 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
341 auto SuccSUnit = Succ.getSUnit(); in NodeSet()

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