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Searched refs:getReg (Results 1 – 25 of 659) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp82 return MIB.buildSub(Ty, Base, Ctlz).getReg(0); in buildLogBase2()
210 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
211 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
215 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
216 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
242 Register Reg = MO.getReg(); in matchCombineConcatVectors()
251 Ops.push_back(BuildVecMO.getReg()); in matchCombineConcatVectors()
260 assert(MRI.getType(Undef->getOperand(0).getReg()) == in matchCombineConcatVectors()
267 Ops.push_back(Undef->getOperand(0).getReg()); in matchCombineConcatVectors()
280 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
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H A DGISelKnownBits.cpp39 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
58 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
190 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
225 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
264 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
266 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
273 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
275 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
285 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
291 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
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H A DLegalizerHelper.cpp238 VRegs.push_back(MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0)); in extractVectorParts()
248 MIRBuilder.buildMergeLikeInstr(LeftoverTy, Pieces).getReg(0)); in extractVectorParts()
322 Regs[StartIdx + I] = MI.getOperand(I).getReg(); in getUnmergeResults()
362 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); in buildLCMMergePieces()
364 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
371 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); in buildLCMMergePieces()
409 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
411 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); in buildLCMMergePieces()
427 Remerge[I] = MIRBuilder.buildMergeLikeInstr(NarrowTy, SubMerge).getReg(0); in buildLCMMergePieces()
605 Register VReg = MI.getOperand(0).getReg(); in isLibCallInTailPosition()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp123 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
124 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
138 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
139 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
150 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
161 Register Reg = Op.getReg(); in applyBank()
308 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
313 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
464 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
490 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
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H A DSIOptimizeExecMasking.cpp101 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec()
102 return MI.getOperand(0).getReg(); in isCopyFromExec()
116 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec()
117 return MI.getOperand(1).getReg(); in isCopyToExec()
141 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
142 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
144 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
145 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
157 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
158 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
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H A DAMDGPULegalizerInfo.cpp1850 return B.buildUnmerge(S32, Dst).getReg(1); in getSegmentAperture()
1881 B.buildConstant(LLT::scalar(64), Offset).getReg(0)); in getSegmentAperture()
1883 return B.buildLoad(S32, LoadAddr, *MMO).getReg(0); in getSegmentAperture()
1903 B.buildConstant(LLT::scalar(64), StructOffset).getReg(0)); in getSegmentAperture()
1904 return B.buildLoad(S32, LoadAddr, *MMO).getReg(0); in getSegmentAperture()
1934 Register Dst = MI.getOperand(0).getReg(); in legalizeAddrSpaceCast()
1935 Register Src = MI.getOperand(1).getReg(); in legalizeAddrSpaceCast()
1973 B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src, FlatNull.getReg(0)); in legalizeAddrSpaceCast()
1974 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1988 Register SrcAsInt = B.buildPtrToInt(S32, Src).getReg(0); in legalizeAddrSpaceCast()
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H A DSIShrinkInstructions.cpp99 Register Reg = Src0.getReg(); in foldImmediates()
151 Register Reg = MO.getReg(); in shouldShrinkTrue16()
315 unsigned Vgpr = TRI->getHWRegIndex(Op.getReg()); in shrinkMIMG()
316 unsigned Dwords = TRI->getRegSizeInBits(Op.getReg(), *MRI) / 32; in shrinkMIMG()
401 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma()
403 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
429 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
466 MI.getOperand(0).getReg()) in shrinkMadFma()
524 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
525 MRI->setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
116 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
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H A DSystemZTargetStreamer.h35 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
36 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
39 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
40 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
H A DSystemZShortenInst.cpp79 Register Reg = MI.getOperand(0).getReg(); in shortenIIF()
111 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { in shortenOn0()
121 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn01()
122 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenOn01()
133 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn001()
134 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
135 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) { in shortenOn001()
159 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenFPConv()
160 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenFPConv()
185 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 && in shortenFusedFPOp()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp226 Register Dst = MI.getOperand(0).getReg(); in matchREV()
227 Register Src = MI.getOperand(1).getReg(); in matchREV()
256 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
261 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
262 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
277 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
282 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
283 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
293 Register Dst = MI.getOperand(0).getReg(); in matchZip()
298 Register V1 = MI.getOperand(1).getReg(); in matchZip()
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H A DAArch64InstructionSelector.cpp656 return RegSequence.getReg(0); in createTuple()
689 getIConstantVRegValWithLookThrough(Root.getReg(), MRI, true); in getImmedFromMO()
708 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
726 if (!MO.getReg().isVirtual()) { in unsupportedBinOp()
731 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
870 RegOp.setReg(SubRegCopy.getReg(0)); in copySubReg()
874 if (!I.getOperand(0).getReg().isPhysical()) in copySubReg()
875 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
888 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
889 Register SrcReg = I.getOperand(1).getReg(); in getRegClassesForCopy()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp145 CopyOperands->Destination->getReg().asMCReg()); in invalidateRegister()
146 RegsToInvalidate.insert(CopyOperands->Source->getReg().asMCReg()); in invalidateRegister()
171 markRegsUnavailable({CopyOperands->Destination->getReg().asMCReg()}, in clobberRegister()
187 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in trackCopy()
188 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in trackCopy()
242 Register AvailSrc = CopyOperands->Source->getReg(); in findAvailBackwardCopy()
243 Register AvailDef = CopyOperands->Destination->getReg(); in findAvailBackwardCopy()
272 Register AvailSrc = CopyOperands->Source->getReg(); in findAvailCopy()
273 Register AvailDef = CopyOperands->Destination->getReg(); in findAvailCopy()
389 MCRegister PreviousSrc = CopyOperands->Source->getReg().asMCReg(); in isNopCopy()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp111 printRegName(O, Dst.getReg()); in printInst()
113 printRegName(O, MO1.getReg()); in printInst()
116 printRegName(O, MO2.getReg()); in printInst()
133 printRegName(O, Dst.getReg()); in printInst()
135 printRegName(O, MO1.getReg()); in printInst()
151 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
165 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
170 printRegName(O, MI->getOperand(1).getReg()); in printInst()
180 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
194 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h32 Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); } in getReg() function
44 Register getPointerReg() const { return getOperand(1).getReg(); } in getPointerReg()
82 Register getDstReg() const { return getOperand(0).getReg(); } in getDstReg()
133 Register getValueReg() const { return getOperand(0).getReg(); } in getValueReg()
146 Register getSourceReg() const { return getOperand(getNumDefs()).getReg(); } in getSourceReg()
161 Register getSourceReg(unsigned I) const { return getReg(I + 1); } in getSourceReg()
202 Register getBaseReg() const { return getReg(1); } in getBaseReg()
203 Register getOffsetReg() const { return getReg(2); } in getOffsetReg()
221 Register getCondReg() const { return getReg(1); } in getCondReg()
222 Register getTrueReg() const { return getReg(2); } in getTrueReg()
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H A DLegalizationArtifactCombiner.h63 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
64 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
117 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
118 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
136 SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0); in tryCombineZExt()
138 TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0); in tryCombineZExt()
179 Register DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
180 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineSExt()
192 TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0); in tryCombineSExt()
237 Register DstReg = MI.getOperand(0).getReg(); in tryCombineTrunc()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
119 if (!RT.getReg().isVirtual()) in checkOpConstraints()
123 (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8)) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
209 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
220 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
H A DPPCMIPeephole.cpp166 Register Reg = Op->getReg(); in getVRegDefOrNull()
295 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs()
303 Register Reg = Instr->getOperand(1).getReg(); in collectUnprimedAccPHIs()
340 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs()
347 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
365 PrimedAccPHI->getOperand(0).getReg(), false), in convertUnprimedAccPHIs()
454 Register Src = MI.getOperand(1).getReg(); in simplifyCode()
455 Register Dst = MI.getOperand(0).getReg(); in simplifyCode()
491 Register MIDestReg = MI.getOperand(0).getReg(); in simplifyCode()
530 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); in simplifyCode()
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H A DPPCVSXCopy.cpp94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
123 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp238 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
273 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
283 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
296 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
303 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
317 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
318 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
326 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
327 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
336 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp57 GR->add(GV, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
64 auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
69 BuildVec->getOperand(1 + i).getReg()); in addConstantsToTrack()
71 GR->add(Const, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
77 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
85 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
88 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg); in addConstantsToTrack()
106 MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg()); in foldConstantsIntoIntrinsics()
111 if (MRI.use_empty(ConstMI->getOperand(0).getReg())) in foldConstantsIntoIntrinsics()
129 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
261 Register T = MO.getReg(); in partitionRegisters()
374 Register Rs = MI->getOperand(1).getReg(); in profit()
375 Register Rt = MI->getOperand(2).getReg(); in profit()
442 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
501 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
509 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
537 Register R = MD.getReg(); in collectIndRegsForLoop()
553 Register T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
601 Register R = Op.getReg(); in createHalfInstr()
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H A DHexagonPeephole.cpp135 Register DstReg = Dst.getReg(); in runOnMachineFunction()
136 Register SrcReg = Src.getReg(); in runOnMachineFunction()
155 Register DstReg = Dst.getReg(); in runOnMachineFunction()
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
172 Register DstReg = Dst.getReg(); in runOnMachineFunction()
173 Register SrcReg = Src1.getReg(); in runOnMachineFunction()
183 Register DstReg = Dst.getReg(); in runOnMachineFunction()
184 Register SrcReg = Src.getReg(); in runOnMachineFunction()
205 Register DstReg = Dst.getReg(); in runOnMachineFunction()
206 Register SrcReg = Src.getReg(); in runOnMachineFunction()
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