Home
last modified time | relevance | path

Searched refs:getPhysRegBaseClass (Results 1 – 9 of 9) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp190 : TRI.getPhysRegBaseClass(SrcReg); in getCopyRegClasses()
197 : TRI.getPhysRegBaseClass(DstReg); in getCopyRegClasses()
H A DSIRegisterInfo.cpp125 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in SGPRSpillBuilder()
2785 RC = getPhysRegBaseClass(Reg); in isSGPRReg()
2902 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegBaseClass(Reg); in getRegClassForReg()
3112 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32); in get32BitRegister()
H A DSIInstrInfo.cpp720 const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()
726 (RI.getRegSizeInBits(*RI.getPhysRegBaseClass(SrcReg)) == 16))) { in copyPhysReg()
738 RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()
929 const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()
3186 RI.isSGPRClass(RI.getPhysRegBaseClass(Src0->getReg())))) || in FoldImmediate()
3203 RI.isSGPRClass(RI.getPhysRegBaseClass(Src1->getReg()))) || in FoldImmediate()
4960 return RI.getPhysRegBaseClass(Reg); in getOpRegClass()
8436 const TargetRegisterClass *regClass = RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity()
8466 const TargetRegisterClass *regClass = RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity()
H A DSIFrameLowering.cpp337 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in PrologEpilogSGPRSpillBuilder()
1321 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); in processFunctionBeforeFrameFinalized()
H A DGCNHazardRecognizer.cpp1213 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()
1294 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) in fixVcmpxExecWARHazard()
H A DAMDGPUISelDAGToDAG.cpp358 return TRI->getPhysRegBaseClass(Reg); in getOperandRegClass()
1434 auto RC = TRI.getPhysRegBaseClass(Reg); in IsCopyFromSGPR()
H A DSIWholeQuadMode.cpp610 TRI->hasVectorRegisters(TRI->getPhysRegBaseClass(Reg))) { in scanInstructions()
H A DSIISelLowering.cpp12344 Ret.second = TRI->getPhysRegBaseClass(Ret.first); in getRegForInlineAsmConstraint()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h700 virtual const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const { in getPhysRegBaseClass() function