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Searched refs:getOrder (Results 1 – 25 of 29) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/tools/llvm-tapi-diff/
H A DDiffEngine.h72 InterfaceInputOrder getOrder() const { return Order; } in getOrder() function
95 InterfaceInputOrder getOrder() const { return Order; } in getOrder() function
H A DDiffEngine.cpp443 return ValA.getOrder() < ValB.getOrder(); in sortTargetValues()
446 return ValA.getOrder() == ValB.getOrder() && ValA.getVal() < ValB.getVal(); in sortTargetValues()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp760 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
973 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
986 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1012 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
1034 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
H A DSDNodeDbgValue.h219 unsigned getOrder() const { return Order; } in getOrder() function
259 unsigned getOrder() const { return Order; } in getOrder() function
H A DSelectionDAGDumper.cpp856 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
H A DAllocationOrder.h111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
H A DRegAllocBase.cpp128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
H A DRegAllocFast.cpp807 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
862 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
1004 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1250 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()
1251 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
H A DBreakFalseDeps.cpp156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
H A DCriticalAntiDepBreaker.cpp406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
H A DAggressiveAntiDepBreaker.cpp618 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
H A DRegAllocGreedy.cpp530 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit()
544 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in getOrderLimit()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1048 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1084 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1093 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1249 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1400 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1413 if (RC.getOrder(oi).empty()) in runTargetDesc()
H A DCodeGenRegisters.h429 ArrayRef<Record*> getOrder(unsigned No = 0) const {
H A DAsmMatcherEmitter.cpp1234 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1310 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses()
1311 RC.getOrder().end())]; in buildRegisterClasses()
/openbsd-src/gnu/llvm/llvm/include/llvm/Passes/
H A DStandardInstrumentations.h322 std::vector<std::string> &getOrder() { return Order; } in getOrder() function
323 const std::vector<std::string> &getOrder() const { return Order; } in getOrder() function
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
/openbsd-src/gnu/llvm/llvm/lib/Passes/
H A DStandardInstrumentations.cpp535 std::vector<std::string>::const_iterator BI = Before.getOrder().begin(); in report()
536 std::vector<std::string>::const_iterator BE = Before.getOrder().end(); in report()
537 std::vector<std::string>::const_iterator AI = After.getOrder().begin(); in report()
538 std::vector<std::string>::const_iterator AE = After.getOrder().end(); in report()
659 FD.getOrder().emplace_back(BBName); in generateFunctionData()
662 Data.getOrder().emplace_back(F.getName()); in generateFunctionData()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp133 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const { in getOrder() function in __anon24d030b90111::PostOrderLoopTraversal
1814 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder(); in Expand()
/openbsd-src/gnu/llvm/llvm/include/llvm/Frontend/OpenMP/
H A DOMPIRBuilder.h1961 unsigned getOrder() const { return Order; } in getOrder() function
/openbsd-src/gnu/llvm/llvm/lib/Frontend/OpenMP/
H A DOMPIRBuilder.cpp4838 GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
4841 OrderedEntries[E.getOrder()] = std::make_pair(&E, EntryInfo); in createOffloadEntriesAndInfoMetadata()
4863 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
4867 OrderedEntries[E.getOrder()] = std::make_pair(&E, varInfo); in createOffloadEntriesAndInfoMetadata()
/openbsd-src/gnu/llvm/clang/lib/CodeGen/
H A DCGAtomic.cpp850 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr()

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