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Searched refs:getOperand (Results 1 – 25 of 1068) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
54 const MCOperand &LSB = MI.getOperand(Idx + 1); in getImmOpValueMSBSize()
80 .addOperand(MI.getOperand(0)) in expandJBTF()
87 .addOperand(MI.getOperand(1)) in expandJBTF()
88 .addOperand(MI.getOperand(2)); in expandJBTF()
90 TmpInst = MCInstBuilder(CSKY::JMPI32).addOperand(MI.getOperand(2)); in expandJBTF()
105 .addOperand(MI.getOperand(0)) in expandNEG()
106 .addOperand(MI.getOperand(1)); in expandNEG()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
130 Register AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
186 Register OldFMAReg = MI.getOperand(0).getReg(); in processBlock()
190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
191 Register Reg3 = MI.getOperand(3).getReg(); in processBlock()
218 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg(); in processBlock()
219 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg(); in processBlock()
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H A DPPCMIPeephole.cpp182 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
185 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
186 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
191 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
192 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
195 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
295 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs()
303 Register Reg = Instr->getOperand(1).getReg(); in collectUnprimedAccPHIs()
340 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs()
347 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp149 Register DstReg = MI.getOperand(0).getReg(); in expandArith()
150 Register SrcReg = MI.getOperand(2).getReg(); in expandArith()
151 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith()
152 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
153 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
154 bool ImpIsDead = MI.getOperand(3).isDead(); in expandArith()
170 MIBHI->getOperand(3).setIsDead(); in expandArith()
173 MIBHI->getOperand(4).setIsKill(); in expandArith()
182 Register DstReg = MI.getOperand(0).getReg(); in expandLogic()
183 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic()
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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp49 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
79 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
84 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
85 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
87 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
88 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
103 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
130 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
132 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
133 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZTargetStreamer.h31 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
32 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
35 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
36 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
37 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
38 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
39 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
40 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
41 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
42 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
H A DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp101 const MCOperand &Dst = MI->getOperand(0); in printInst()
102 const MCOperand &MO1 = MI->getOperand(1); in printInst()
103 const MCOperand &MO2 = MI->getOperand(2); in printInst()
104 const MCOperand &MO3 = MI->getOperand(3); in printInst()
124 const MCOperand &Dst = MI->getOperand(0); in printInst()
125 const MCOperand &MO1 = MI->getOperand(1); in printInst()
126 const MCOperand &MO2 = MI->getOperand(2); in printInst()
151 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
165 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
166 MI->getOperand(3).getImm() == -4) { in printInst()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp83 printOperand(MI->getOperand(OpNum), O); in printOperand()
88 OS << getRegisterName(MI->getOperand(OpNum).getReg()); in printMemOperand()
95 const MCOperand &MC = MI->getOperand(OpNum); in printBranchTarget()
96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
110 const MCOperand &MC = MI->getOperand(OpNum); in printJumpTarget()
126 const MCOperand &MC = MI->getOperand(OpNum); in printCallOperand()
141 const MCOperand &MC = MI->getOperand(OpNum); in printL32RTarget()
143 int64_t Value = MI->getOperand(OpNum).getImm(); in printL32RTarget()
159 if (MI->getOperand(OpNum).isImm()) { in printImm8_AsmOperand()
160 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm8_AsmOperand()
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/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp104 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
105 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
135 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
171 N->getOperand(2) }; in Select()
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 N->getOperand(2) }; in Select()
184 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
185 N->getOperand(2), N->getOperand(3) }; in Select()
191 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp52 MI.getOperand(3).getMetadata()->getOperand(0)) in addConstantsToTrack()
57 GR->add(GV, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
64 auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
69 BuildVec->getOperand(1 + i).getReg()); in addConstantsToTrack()
71 GR->add(Const, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
76 assert(MI.getOperand(2).isReg() && "Reg operand is expected"); in addConstantsToTrack()
77 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
85 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
88 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg); in addConstantsToTrack()
104 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
98 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
112 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
124 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
143 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
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H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp39 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
42 return Align(MI->getOperand(2).getImm()); in computeKnownAlignment()
45 int FrameIdx = MI->getOperand(1).getIndex(); in computeKnownAlignment()
58 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
190 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
210 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?"); in computeKnownBitsImpl()
224 const MachineOperand &Src = MI.getOperand(Idx); in computeKnownBitsImpl()
259 int FrameIdx = MI.getOperand(1).getIndex(); in computeKnownBitsImpl()
264 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
266 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
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H A DCombinerHelper.cpp210 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
211 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
215 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
216 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
260 assert(MRI.getType(Undef->getOperand(0).getReg()) == in matchCombineConcatVectors()
267 Ops.push_back(Undef->getOperand(0).getReg()); in matchCombineConcatVectors()
280 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
311 LLT DstType = MRI.getType(MI.getOperand(0).getReg()); in matchCombineShuffleVector()
312 Register Src1 = MI.getOperand(1).getReg(); in matchCombineShuffleVector()
348 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); in matchCombineShuffleVector()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp60 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
62 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
68 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
93 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
94 unsigned RegOp1 = Inst.getOperand(1).getReg(); in LowerCompactBranch()
114 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
115 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
237 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
259 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue1SImm16()
281 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMR6()
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp94 const MachineOperand &HiOp1 = Hi.getOperand(1); in INITIALIZE_PASS()
103 Register HiDestReg = Hi.getOperand(0).getReg(); in INITIALIZE_PASS()
111 const MachineOperand &LoOp2 = Lo->getOperand(2); in INITIALIZE_PASS()
142 Hi.getOperand(1).setOffset(Offset); in foldOffset()
144 Lo.getOperand(2).setOffset(Offset); in foldOffset()
146 MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg()); in foldOffset()
177 Register Rs = TailAdd.getOperand(1).getReg(); in foldLargeOffset()
178 Register Rt = TailAdd.getOperand(2).getReg(); in foldLargeOffset()
190 MachineOperand &AddiImmOp = OffsetTail.getOperand(2); in foldLargeOffset()
195 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); in foldLargeOffset()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp126 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
128 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; in expandMOVImm()
129 uint64_t Imm = MI.getOperand(1).getImm(); in expandMOVImm()
152 .add(MI.getOperand(0)) in expandMOVImm()
160 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
170 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
171 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
194 const MachineOperand &Dest = MI.getOperand(0); in expandCMP_SWAP()
195 Register StatusReg = MI.getOperand(1).getReg(); in expandCMP_SWAP()
196 bool StatusDead = MI.getOperand(1).isDead(); in expandCMP_SWAP()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp103 MI->getOperand(1).getReg().isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
104 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY()
124 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) { in findLoopComponents()
129 T.getOperand(2).getMBB() == Header) { in findLoopComponents()
153 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents()
162 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents()
165 (LoopPhi->getOperand(2).getMBB() != Latch && in findLoopComponents()
166 LoopPhi->getOperand(4).getMBB() != Latch)) { in findLoopComponents()
172 Register StartReg = LoopPhi->getOperand(2).getMBB() == Latch in findLoopComponents()
173 ? LoopPhi->getOperand(3).getReg() in findLoopComponents()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
77 << getRegisterName(MI->getOperand(1).getReg()) << "], %" in printMemoryLoadIncrement()
78 << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
84 << "], %" << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp107 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode()
262 .add(I.getOperand(0)) in buildUnalignedStore()
300 isRegInGprb(I.getOperand(0).getReg(), MRI)) { in select()
302 .add(I.getOperand(0)) in select()
303 .add(I.getOperand(1)) in select()
304 .add(I.getOperand(2)); in select()
307 Mul->getOperand(3).setIsDead(true); in select()
308 Mul->getOperand(4).setIsDead(true); in select()
327 .add(I.getOperand(1)) in select()
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H A DMipsSEISelLowering.cpp412 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
413 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
414 Op->getOperand(2)); in lowerSELECT()
481 SDValue Op0 = N->getOperand(0); in performANDCombine()
482 SDValue Op1 = N->getOperand(1); in performANDCombine()
501 SDValue Op0Op2 = Op0->getOperand(2); in performANDCombine()
508 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; in performANDCombine()
551 N = N->getOperand(0); in isVectorAllOnes()
575 if (isVectorAllOnes(N->getOperand(0))) in isBitwiseInverse()
576 return N->getOperand(1) == OfNode; in isBitwiseInverse()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp915 LHS = N.getOperand(0); in isSetCCEquivalent()
916 RHS = N.getOperand(1); in isSetCCEquivalent()
917 CC = N.getOperand(2); in isSetCCEquivalent()
924 LHS = N.getOperand(1); in isSetCCEquivalent()
925 RHS = N.getOperand(2); in isSetCCEquivalent()
926 CC = N.getOperand(3); in isSetCCEquivalent()
930 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || in isSetCCEquivalent()
931 !TLI.isConstFalseVal(N.getOperand(3))) in isSetCCEquivalent()
938 LHS = N.getOperand(0); in isSetCCEquivalent()
939 RHS = N.getOperand(1); in isSetCCEquivalent()
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