Searched refs:getOpRegClass (Results 1 – 6 of 6) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 342 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
346 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
2094 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
4365 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
4640 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx); in verifyInstruction()
4950 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
5879 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
5882 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
5885 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
5889 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
[all …]
|
| H A D | SIInstrInfo.h | 916 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
942 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
|
| H A D | SIFixSGPRCopies.cpp | 651 if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) { in runOnMachineFunction()
|
| H A D | SIInsertWaitcnts.cpp | 522 const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo); in getRegInterval()
|
| H A D | SIRegisterInfo.cpp | 2361 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
|
| H A D | SIISelLowering.cpp | 12065 uint32_t DstSize = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddIMGInit()
12070 Register PrevDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()
12081 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()
|