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Searched refs:getInstr (Results 1 – 25 of 99) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp31 if (QII->mayBeCurLoad(*SUd->getInstr())) in hasDependence()
34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) { in SchedulingCost()
H A DHexagonSubtarget.cpp268 MachineInstr &MI1 = *SU.getInstr(); in apply()
277 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
305 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
309 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
329 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
332 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
353 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
393 MachineInstr &L0 = *S0.getInstr(); in apply()
406 MachineInstr &L1 = *S1.getInstr(); in apply()
445 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
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H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
113 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp422 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
516 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
517 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
518 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
673 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
759 MachineInstr &TempMI = *TempSU->getInstr(); in canPromoteToNewValueStore()
772 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
826 MachineInstr &PacketMI = *PacketSU->getInstr(); in canPromoteToNewValue()
859 const MachineInstr &PI = *PacketSU->getInstr(); in canPromoteToDotNew()
1325 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp299 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
302 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
303 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
304 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
309 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
314 Pred.getInstr()->getDebugExpression()); in beginFunction()
321 if (IsDescribedByReg(I->getInstr())) in beginFunction()
323 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
330 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
332 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
H A DDbgEntityHistoryCalculator.cpp79 Entries.back().getInstr()->isEquivalentDbgInstr(MI)) { in startDbgValue()
81 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
95 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
197 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
199 ? HistoryMapEntries[EndIndex].getInstr() in trimLocationRanges()
264 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
338 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
340 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
343 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
347 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
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/openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/
H A DSnippetGenerator.cpp48 if (Variant.getInstr().hasMemoryOperands()) { in generateConfigurations()
59 for (const auto &Op : Variant.getInstr().Operands) { in generateConfigurations()
122 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
132 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
147 Variant.getInstr(), Variant.getInstr(), ForbiddenRegisters); in generateSelfAliasingCodeTemplates()
275 for (const Variable &Var : IT.getInstr().Variables) { in randomizeUnsetVariables()
278 if (auto Err = randomizeMCOperand(State, IT.getInstr(), Var, in randomizeUnsetVariables()
H A DSerialSnippetGenerator.cpp51 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode); in computeAliasingInstructions()
119 Variant.getInstr(), Variant.getInstr(), ForbiddenRegisters); in appendCodeTemplates()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates()
167 getExecutionModes(Variant.getInstr(), ForbiddenRegisters); in generateCodeTemplates()
H A DParallelSnippetGenerator.cpp152 const Instruction &Instr = IT.getInstr(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
220 const Instruction &Instr = IT.getInstr(); in generateSingleSnippetForInstrAvoidingDefUseOverlap()
260 for (const auto &Op : IT.getInstr().Operands) { in generateSnippetForInstrAvoidingDefUseOverlap()
288 if (!hasVariablesWithTiedOperands(IT.getInstr())) in generateSnippetForInstrAvoidingDefUseOverlap()
297 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp154 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
155 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
188 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
213 MachineInstr *MI = SU->getInstr(); in getAluKind()
287 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
316 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
318 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
387 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
436 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DAMDGPUIGroupLP.cpp152 << *SU.getInstr()); in add()
193 assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER || in resetEdges()
194 SU.getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER || in resetEdges()
195 SU.getInstr()->getOpcode() == AMDGPU::IGLP_OPT); in resetEdges()
327 return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER; in reset()
372 if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in makePipeline()
904 if (A == B || A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in link()
926 if (A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in link()
952 MachineInstr &MI = *SU.getInstr(); in canAddSU()
1020 unsigned Opc = R->getInstr()->getOpcode(); in apply()
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H A DGCNDPPCombine.cpp236 if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) { in createDPPInst()
281 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
304 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
323 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
324 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
389 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
392 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
393 return DPPInst.getInstr(); in createDPPInst()
583 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp252 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
319 RPTracker.setPos(SU->getInstr()); in initRegPressure()
400 TopRPTracker.setPos(SU->getInstr()); in schedule()
1125 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1137 if (!SIInstrInfo::isEXP(*SuccSU->getInstr())) { in colorExports()
1322 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1351 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1793 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1803 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1824 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DMacroFusion.cpp93 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
94 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
160 if (DAG->ExitSU.getInstr()) in apply()
168 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
187 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DMachinePipeliner.cpp637 OrderedInsts.push_back(SU->getInstr()); in schedule()
638 Cycles[SU->getInstr()] = Cycle; in schedule()
639 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
765 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
790 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
866 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
922 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
924 if (I.getInstr()->isPHI()) { in updatePhiDependences()
947 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
952 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
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H A DScheduleDAGInstrs.cpp236 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
244 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
266 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
269 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); in addPhysRegDataDeps()
274 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
289 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
314 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
318 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
393 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
441 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
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H A DVLIWMachineScheduler.cpp109 if (!SU || !SU->getInstr()) in isResourceAvailable()
114 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
116 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
162 switch (SU->getInstr()->getOpcode()) { in reserveResources()
164 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
186 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
326 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
365 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
432 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
532 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta, in readyQueueVerboseDump()
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H A DSlotIndexes.cpp125 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
138 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
208 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
245 if (ILE.getInstr()) { in dump()
246 dbgs() << *ILE.getInstr(); in dump()
H A DMachineScheduler.cpp806 MachineInstr *MI = SU->getInstr(); in schedule()
954 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1145 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); in updatePressureDiffs()
1174 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1179 << *SU->getInstr(); in updatePressureDiffs()
1190 if (EntrySU.getInstr() != nullptr) in dump()
1199 if (SchedModel.mustBeginGroup(SU.getInstr()) && in dump()
1200 SchedModel.mustEndGroup(SU.getInstr())) in dump()
1206 if (ExitSU.getInstr() != nullptr) in dump()
1371 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp19 const auto Op = IT.getInstr().Operands[OpIdx]; in setMemOp()
77 if (IT.getInstr().hasTiedRegisters()) in fillMemoryOperands()
80 const auto DispOp = IT.getInstr().Operands[DispOpIdx]; in fillMemoryOperands()
/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp374 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
377 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
389 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
420 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
425 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
428 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
439 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and "); in ExpandMOVSZX_RM()
457 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVSZX_RM()
475 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandPUSH_POP()
511 auto MI = MIB.getInstr(); in ExpandMOVEM()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp47 MachineInstr *MI = SU->getInstr(); in getHazardType()
90 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
185 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
257 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp66 MachineInstr *Instr0 = TryCand.SU->getInstr(); in tryCandidate()
67 MachineInstr *Instr1 = Cand.SU->getInstr(); in tryCandidate()

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