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/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/g++.old-deja/g++.oliva/
H A DChangeLog83 1999-08-25 Alexandre Oliva <oliva@dcc.unicamp.br>
87 1999-08-06 Alexandre Oliva <oliva@dcc.unicamp.br>
93 1999-08-05 Alexandre Oliva <oliva@dcc.unicamp.br>
98 1999-08-03 Alexandre Oliva <oliva@dcc.unicamp.br>
104 1999-07-20 Alexandre Oliva <oliva@dcc.unicamp.br>
108 1999-07-17 Alexandre Oliva <oliva@dcc.unicamp.br>
112 1999-07-13 Alexandre Oliva <oliva@dcc.unicamp.br>
122 1999-07-05 Alexandre Oliva <oliva@dcc.unicamp.br>
130 1999-07-03 Alexandre Oliva <oliva@dcc.unicamp.br>
136 1999-07-02 Alexandre Oliva <oliva@dcc.unicamp.br>
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c351 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
356 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
357 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
358 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
359 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
360 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
361 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
401 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
407 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
409 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
H A Ddcn30_hubp.h270 struct dc_plane_dcc_param *dcc,
285 struct dc_plane_dcc_param *dcc);
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_hubp.c48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
/openbsd-src/sys/arch/armv7/vexpress/
H A Dsysreg.c103 int dcc, site, position, device; in sysconf_function() local
105 dcc = 0; in sysconf_function()
113 (dcc << 26) | (function << 20) | (site << 16) | in sysconf_function()
/openbsd-src/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c266 const struct dc_plane_dcc_param *dcc, in validate_dcc()
277 if (!dcc->enable) in validate_dcc()
300 if (dcc->independent_64b_blks == 0 && in validate_dcc()
313 struct dc_plane_dcc_param *dcc, in fill_gfx9_plane_attributes_from_modifiers()
328 dcc->enable = 1; in fill_gfx9_plane_attributes_from_modifiers()
329 dcc->meta_pitch = afb->base.pitches[1]; in fill_gfx9_plane_attributes_from_modifiers()
330 dcc->independent_64b_blks = independent_64b_blks; in fill_gfx9_plane_attributes_from_modifiers()
333 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; in fill_gfx9_plane_attributes_from_modifiers()
335 dcc->dcc_ind_blk = hubp_ind_block_128b; in fill_gfx9_plane_attributes_from_modifiers()
337 dcc in fill_gfx9_plane_attributes_from_modifiers()
265 validate_dcc(struct amdgpu_device * adev,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const union dc_tiling_info * tiling_info,const struct dc_plane_dcc_param * dcc,const struct dc_plane_address * address,const struct plane_size * plane_size) validate_dcc() argument
312 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const struct plane_size * plane_size,union dc_tiling_info * tiling_info,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address,const bool force_disable_dcc) fill_gfx9_plane_attributes_from_modifiers() argument
760 amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const uint64_t tiling_flags,union dc_tiling_info * tiling_info,struct plane_size * plane_size,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address,bool tmz_surface,bool force_disable_dcc) amdgpu_dm_plane_fill_plane_buffer_attributes() argument
[all...]
H A Damdgpu_dm_plane.h49 struct dc_plane_dcc_param *dcc,
/openbsd-src/gnu/usr.bin/gcc/contrib/
H A DChangeLog588 1999-07-28 Alexandre Oliva <oliva@dcc.unicamp.br>
593 1999-07-27 Alexandre Oliva <oliva@dcc.unicamp.br>
603 1999-07-17 Alexandre Oliva <oliva@dcc.unicamp.br>
614 1999-07-03 Alexandre Oliva <oliva@dcc.unicamp.br>
619 1999-06-12 Alexandre Oliva <oliva@dcc.unicamp.br>
643 1999-01-07 Alexandre Oliva <oliva@dcc.unicamp.br>
652 1998-11-29 Alexandre Oliva <oliva@dcc.unicamp.br>
657 1998-11-28 Alexandre Oliva <oliva@dcc.unicamp.br>
661 1998-11-27 Alexandre Oliva <oliva@dcc.unicamp.br>
666 1998-11-25 Alexandre Oliva <oliva@dcc.unicamp.br>
[all …]
H A Dtest_installed64 by Alexandre Oliva <oliva@dcc.unicamp.br>
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
541 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
545 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
547 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
H A Ddcn10_hubp.h711 struct dc_plane_dcc_param *dcc,
732 struct dc_plane_dcc_param *dcc);
/openbsd-src/sys/dev/pci/drm/i915/gt/
H A Dintel_ggtt_fencing.c669 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
680 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
687 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
694 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
713 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
/openbsd-src/regress/lib/libcrypto/x509/bettertls/certificates/
H A D2448.crt18 kqzbA7VpanqX1Dlu6bKJvNh/ib3jipA01wCeQin9PixfuWRYFUCiZtiQXWhl+dcc
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c330 struct dc_plane_dcc_param *dcc) in hubp2_program_size() argument
348 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
350 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp2_program_size()
353 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
358 if (!dcc->enable) { in hubp2_program_size()
540 struct dc_plane_dcc_param *dcc, in hubp2_program_surface_config() argument
546 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp2_program_surface_config()
548 hubp2_program_size(hubp, format, plane_size, dcc); in hubp2_program_surface_config()
H A Ddcn20_hubp.h328 struct dc_plane_dcc_param *dcc);
345 struct dc_plane_dcc_param *dcc,
/openbsd-src/gnu/usr.bin/binutils/binutils/
H A Dacinclude.m419 ## by Alexandre Oliva <oliva@dcc.unicamp.br>
/openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dmem_input.h161 struct dc_plane_dcc_param *dcc,
H A Dhubp.h141 struct dc_plane_dcc_param *dcc,
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_mem_input.c636 struct dc_plane_dcc_param *dcc, in dce_mi_program_surface_config() argument
657 struct dc_plane_dcc_param *dcc, in dce60_mi_program_surface_config() argument
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h386 unsigned char dcc; member
H A Ddisplay_mode_lib.c184 dml_print("DML PARAMS: dcc = %d\n", pipe_src->dcc); in dml_log_pipe_params()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/core/
H A Ddc_debug.c164 plane_state->dcc.enable, in pre_surface_trace()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c320 * this method requires us to always re-calculate watermark when dcc change in pipe_ctx_to_e2e_pipe_params()
323 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
326 * allow us to disable dcc on the fly without re-calculating WM in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
337 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
990 * this method requires us to always re-calculate watermark when dcc change in dcn_validate_bandwidth()
993 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()
996 * allow us to disable dcc on the fly without re-calculating WM in dcn_validate_bandwidth()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1378 pipes[pipe_cnt].pipe.src.dcc = false; in dcn20_populate_dml_pipes_from_context()
1632 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; in dcn20_populate_dml_pipes_from_context()
1633 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; in dcn20_populate_dml_pipes_from_context()
1636 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; in dcn20_populate_dml_pipes_from_context()
1638 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; in dcn20_populate_dml_pipes_from_context()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/
H A Ddc.h1206 struct dc_plane_dcc_param dcc; member
1264 struct dc_plane_dcc_param dcc; member

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