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Searched refs:ctrl1 (Results 1 – 8 of 8) sorted by relevance

/openbsd-src/gnu/llvm/lldb/include/lldb/Utility/
H A DAnsiTerminal.h70 #define ANSI_1_CTRL(ctrl1) "\033["##ctrl1 ANSI_ESC_END argument
71 #define ANSI_2_CTRL(ctrl1, ctrl2) "\033["##ctrl1 ";"##ctrl2 ANSI_ESC_END argument
/openbsd-src/sys/dev/pci/drm/i915/display/
H A Dintel_dpll_mgr.c1275 pll->state.hw_state.ctrl1 << (id * 6)); in skl_ddi_pll_write_ctrl1()
1343 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1381 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1705 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1712 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_hdmi_pll_dividers()
1714 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); in skl_ddi_hdmi_pll_dividers()
1731 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()
1744 u32 ctrl1; in skl_ddi_dp_set_dpll_hw_state() local
1750 ctrl1 in skl_ddi_dp_set_dpll_hw_state()
[all...]
H A Dintel_dpll_mgr.h203 u32 ctrl1; member
H A Dintel_display.c5322 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); in intel_pipe_config_compare()
/openbsd-src/sys/dev/ic/
H A Dfxpreg.h137 volatile u_int8_t ctrl1; member
H A Dfxp.c1264 cbp->ctrl1 |= 0x80; /* save bad frames */ in fxp_init()
1266 cbp->ctrl1 &= ~0x80; /* discard bad frames */ in fxp_init()
1282 cbp->ctrl1 |= 0x08; /* ci_int = 1 */ in fxp_init()
H A Dbwivar.h119 uint32_t ctrl1; member
/openbsd-src/usr.sbin/npppd/pptp/
H A Dpptpd.c856 pptp_ctrl *ctrl1; in pptpd_ctrl_finished_notify() local
866 ctrl1 = slist_get(&_this->ctrl_list, i); in pptpd_ctrl_finished_notify()
867 if (ctrl1 == ctrl) { in pptpd_ctrl_finished_notify()