Searched refs:buildUndef (Results 1 – 12 of 12) sorted by relevance
653 B.buildUndef(R); in lowerFormalArguments()832 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()837 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()925 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
2036 B.buildUndef(Dst); in legalizeAddrSpaceCast()2352 B.buildUndef(Dst); in legalizeExtractVectorElt()2394 B.buildUndef(Dst); in legalizeInsertVectorElt()2515 B.buildUndef(DstReg); in legalizeGlobalValue()3300 B.buildUndef(DstReg); in loadInputValue()3343 B.buildUndef(DstReg); in legalizeWorkitemIDIntrinsic()4325 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()4335 PackedRegs.resize(6, B.buildUndef(S16).getReg(0)); in handleD16VData()4346 PackedRegs.resize(4, B.buildUndef(S32).getReg(0)); in handleD16VData()4794 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()[all …]
1925 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
242 Register Undef = buildUndef(Op0Ty.getElementType()).getReg(0); in buildPadVectorWithUndefElements()596 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder710 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
364 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()409 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()929 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()940 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()1596 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()3986 MIRBuilder.buildUndef(DstReg); in fewerElementsVectorExtractInsertVectorElt()4379 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); in fewerElementsVectorShuffle()4398 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); in fewerElementsVectorShuffle()4403 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) in fewerElementsVectorShuffle()4931 Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType())); in moreElementsVector()[all …]
258 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()291 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()372 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()1823 B.buildUndef(DstReg); in matchCombineUnmergeUndef()2620 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()2694 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2183 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()2683 MIRBuilder.buildUndef(Undef); in translateLandingPad()3057 EntryBuilder->buildUndef(Reg); in translate()
549 Register Undef = B.buildUndef(SrcTy).getReg(0); in buildCopyToRegs()
414 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()427 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
753 auto Undef = B.buildUndef(SrcTy); in applyDupLane()
1572 auto Undef = MIRBuilder.buildUndef(VecTy); in legalizeFCopySign()
969 MachineInstrBuilder buildUndef(const DstOp &Res);