Searched refs:buildBitcast (Results 1 – 9 of 9) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 145 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
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| H A D | AMDGPULegalizerInfo.cpp | 2878 B.buildBitcast(Dst, Merge); in legalizeBuildVector() 4323 Reg = B.buildBitcast(S32, Reg).getReg(0); in handleD16VData() 4337 return B.buildBitcast(LLT::fixed_vector(3, S32), Reg).getReg(0); in handleD16VData() 4342 Reg = B.buildBitcast(LLT::fixed_vector(2, S32), Reg).getReg(0); in handleD16VData() 4800 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords() 5160 B.buildBitcast(DstReg, ResultRegs[0]); in legalizeImageIntrinsic() 5174 Reg = B.buildBitcast(V2S16, Reg).getReg(0); in legalizeImageIntrinsic() 5464 {B.buildBitcast( in legalizeBVHIntrinsic() 5468 B.buildBitcast( in legalizeBVHIntrinsic() 5472 B.buildBitcast( in legalizeBVHIntrinsic()
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| H A D | AMDGPURegisterBankInfo.cpp | 1732 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32() 2107 B.buildBitcast(MI.getOperand(0).getReg(), Vec); in foldInsertEltToCmpSelect() 2731 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl() 2849 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl() 2884 B.buildBitcast(DstReg, InsHi); in applyMappingImpl() 2901 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
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| H A D | AMDGPUCallLowering.cpp | 82 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 350 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs() 412 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0); in buildCopyFromRegs() 426 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0); in buildCopyFromRegs()
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| H A D | LegalizerHelper.cpp | 1436 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); in coerceToScalar() 1490 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); in bitcastSrc() 1497 MIRBuilder.buildBitcast(MO, CastDst); in bitcastDst() 2681 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); in lowerBitcast() 2746 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt() 2782 MIRBuilder.buildBitcast(Dst, NewVec); in bitcastExtractVectorElt() 2891 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt() 2925 MIRBuilder.buildBitcast(Dst, InsertedElt); in bitcastInsertVectorElt() 6864 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); in lowerExtract()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1233 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore() 1237 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore() 1362 Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0); in legalizeCTPOP()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 129 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 679 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { in buildBitcast() function
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