Searched refs:bitsLE (Results 1 – 19 of 19) sorted by relevance
280 bool bitsLE(EVT VT) const { in bitsLE() function
846 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&862 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
1647 assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatRes_LOAD()1684 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()1696 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()1700 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()1716 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()2007 assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatOp_STORE()
1051 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()1110 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
753 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); in PromoteIntRes_INT_EXTEND()3195 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ANY_EXTEND()3608 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntRes_LOAD()4376 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_SIGN_EXTEND()4408 if (EVT.bitsLE(Lo.getValueType())) { in ExpandIntRes_SIGN_EXTEND_INREG()4697 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ZERO_EXTEND()5173 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntOp_STORE()5343 assert(PromEltVT.bitsLE(NOutVTElem) && in PromoteIntRes_EXTRACT_SUBVECTOR()
1098 EltVT.bitsLE(Op.getValueType()))) && in VerifySDNode()1429 if (VT.bitsLE(Op.getValueType())) in getBoolExtOrTrunc()1446 assert(VT.bitsLE(OpVT) && "Not extending!"); in getZeroExtendInReg()5516 assert(Operand.getValueType().bitsLE(VT) && in getNode()5559 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && in getNode()6297 VT.bitsLE(N1.getValueType()) && in getNode()6311 assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!"); in getNode()6326 assert(EVT.bitsLE(VT) && "Not extending!"); in getNode()6370 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
4527 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && in SimplifySetCC()4838 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
2329 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
5892 if (ExtVT.bitsLE(Load->getMemoryVT())) in SearchForAndLoads()22346 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
1217 bool bitsLE(MVT VT) const { in bitsLE() function
2617 assert((ViaIntVT.bitsLE(XLenVT) || in lowerBUILD_VECTOR()2620 if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) { in lowerBUILD_VECTOR()2780 if (Scalar.getValueType().bitsLE(XLenVT)) { in lowerScalarSplat()2830 auto InnerVT = VT.bitsLE(M1VT) ? VT : M1VT; in lowerScalarInsert()2843 if (!Scalar.getValueType().bitsLE(XLenVT)) in lowerScalarInsert()2860 VT.bitsLE(getLMUL1VT(VT))) in lowerScalarInsert()2865 auto InnerVT = VT.bitsLE(M1VT) ? VT : M1VT; in lowerScalarInsert()5647 if (Scalar.getValueType().bitsLE(XLenVT)) { in LowerINTRINSIC_WO_CHAIN()5994 auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT; in lowerReductionSeq()
1190 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);1194 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1159 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
3438 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
1630 VT.getScalarType().bitsLE(MVT::i16)) in getPreferredVectorAction()5337 return Op.getValueType().bitsLE(VT) ? in getFPExtOrFPRound()
398 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLE(MVT::i32)) in lowerSINT_TO_FP()
1404 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020(); in decomposeMulByConstant()
16954 AVT.bitsLE(Ty); in PerformVECREDUCE_ADDCombine()
26776 assert(MaskVT.bitsLE(Mask.getSimpleValueType()) && "Unexpected mask size!"); in getMaskNode()