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/openbsd-src/gnu/usr.bin/perl/lib/B/
H A DOp_private.pm24 my $name = $B::Op_private::bits{aelem}{7}; # OPpLVAL_INTRO
28 # the bit field at bits 5..6 of OP_AELEM's op_private:
29 my $bf = $B::Op_private::bits{aelem}{6};
36 %B::Op_private::bits
41 which contain information about the per-op meanings of the bits in the
44 =head2 C<%bits>
49 $B::Op_private::bits{aelem}{7} eq 'OPpLVAL_INTRO';
55 $bitfield = $B::Op_private::bits{aelem}{5};
56 $bitfield = $B::Op_private::bits{aelem}{6};
75 # field as raw bits an
[all...]
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td12 bits <5> Vu32;
14 bits <5> Rt32;
16 bits <5> Vdd32;
20 bits <7> Ii;
22 bits <5> Rs32;
24 bits <2> Pd4;
28 bits <5> Rss32;
30 bits <5> Rt32;
32 bits <2> Pd4;
36 bits <11> Ii;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
61 bits<16> Inst;
70 class ANDI_FM_MM16<bits<6> funct> {
71 bits<3> rd;
72 bits<3> rs;
[all …]
H A DMicroMips32r6InstrFormats.td38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
[all …]
H A DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
H A DMipsInstrFormats.td26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
96 bits<4> FormBits = Form.Value;
111 field bits<32> SoftFail = 0;
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
[all …]
H A DMicroMipsDSPInstrFormats.td24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
36 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
37 bits<5> rt;
38 bits<5> rs;
47 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
48 bits<5> rt;
49 bits<5> rs;
[all …]
H A DMips32r6InstrFormats.td43 class OPGROUP<bits<6> Val> {
44 bits<6> Value = Val;
65 class OPCODE2<bits<2> Val> {
66 bits<2> Value = Val;
72 class OPCODE3<bits<3> Val> {
73 bits<3> Value = Val;
77 class OPCODE5<bits<5> Val> {
78 bits<5> Value = Val;
97 class OPCODE6<bits<6> Val> {
98 bits<6> Value = Val;
[all …]
H A DMipsDSPInstrFormats.td39 class Field6<bits<6> val> {
40 bits<6> V = val;
65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
[all …]
H A DMips16InstrFormats.td58 field bits<16> Inst;
59 bits<5> Opcode = 0;
61 // Top 5 bits are the 'opcode' field
65 field bits<16> SoftFail = 0;
75 field bits<32> Inst;
78 field bits<32> SoftFail = 0;
102 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
106 bits<11> imm11;
117 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
121 bits<3> rx;
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
77 field bits<32> Word0;
79 bits<11> src0;
80 bits<1> src0_rel;
81 bits<11> src1;
82 bits<1> src1_rel;
83 bits<3> index_mode = 0;
84 bits<2> pred_sel;
85 bits<1> last;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
15 field bits<32> Inst;
16 field bits<32> SoftFail = 0;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
30 bits<1> PPC970_Cracked = 0;
31 bits<3> PPC970_Unit = 0;
41 bits<1> XFormMemOp = 0;
45 bits<1> Prefixed = 0;
49 // 32 bits to 64 bits.
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/openbsd-src/lib/libm/src/ld80/
H A De_fmodl.c58 struct ieee_ext bits; in fmodl() member
67 sx = ux.bits.ext_sign; in fmodl()
70 if((uy.bits.ext_exp|uy.bits.ext_frach|uy.bits.ext_fracl)==0 || /* y=0 */ in fmodl()
71 (ux.bits.ext_exp == BIAS + LDBL_MAX_EXP) || /* or x not finite */ in fmodl()
72 (uy.bits.ext_exp == BIAS + LDBL_MAX_EXP && in fmodl()
73 ((uy.bits.ext_frach&~LDBL_NBIT)|uy.bits.ext_fracl)!=0)) /* or y is NaN */ in fmodl()
75 if(ux.bits.ext_exp<=uy.bits.ext_exp) { in fmodl()
76 if((ux.bits.ext_exp<uy.bits.ext_exp) || in fmodl()
77 (ux.bits.ext_frach<=uy.bits.ext_frach && in fmodl()
78 (ux.bits.ext_frach<uy.bits.ext_frach || in fmodl()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td32 field bits<24> Inst;
33 field bits<24> SoftFail = 0;
40 field bits<16> Inst;
41 field bits<16> SoftFail = 0;
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
48 bits<4> r;
49 bits<4> s;
50 bits<4> t;
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
63 bits<4> r;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVEInstrFormats.td25 field bits<64> Inst;
30 bits<8> op;
38 bits<1> VE_Vector = 0;
39 bits<1> VE_VLInUse = 0;
40 bits<3> VE_VLIndex = 0;
41 bits<1> VE_VLWithMask = 0;
58 field bits<64> SoftFail = 0;
68 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
70 bits<1> cx = 0;
71 bits<7> sx;
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/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td22 field bits<32> Inst;
27 field bits<32> SoftFail = 0;
47 class Fmt2R<bits<22> op, dag outs, dag ins, string opcstr, string opnstr,
50 bits<5> rj;
51 bits<5> rd;
60 class Fmt3R<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
63 bits<5> rk;
64 bits<5> rj;
65 bits<5> rd;
75 class Fmt3RI2<bits<15> op, dag outs, dag ins, string opcstr, string opnstr,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td9 class AddrMode<bits<5> val> {
10 bits<5> Value = val;
27 field bits<32> SoftFail = 0;
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
45 field bits<32> Inst;
51 field bits<16> Inst;
57 class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
60 bits<26> offset;
68 class I_18_Z_L<bits<3> sop, string asm, dag outs, dag ins, list<dag> pattern>
70 bits<5> rz;
[all …]
H A DCSKYInstrFormats16Instr.td9 class J16<bits<5> sop, string opstr, dag ins>
12 bits<10> offset;
18 class J16_B<bits<5> sop, string opstr>
21 bits<10> offset;
27 class R16_XYZ<bits<2> sop, string opstr, SDNode opnode> : CSKY16Inst<AddrModeNone,
30 bits<3> rz;
31 bits<3> rx;
32 bits<3> ry;
40 class R16_XZ_BINOP<bits<4> op, bits<2> sop, string opstr, PatFrag opnode> : CSKY16Inst<
43 bits<4> rz;
[all …]
/openbsd-src/usr.sbin/nsd/
H A Dbitset.c16 size_t nsd_bitset_size(size_t bits) in nsd_bitset_size() argument
18 if(bits == 0) in nsd_bitset_size()
19 bits++; in nsd_bitset_size()
21 return (bits / CHAR_BIT) + ((bits % CHAR_BIT) != 0) + sizeof(size_t); in nsd_bitset_size()
32 memset(bset->bits, 0, sz); in nsd_bitset_zero()
35 void nsd_bitset_init(struct nsd_bitset *bset, size_t bits) in nsd_bitset_init() argument
38 if (bits == 0) in nsd_bitset_init()
39 bits++; in nsd_bitset_init()
41 bset->size = bits; in nsd_bitset_init()
51 return (bset->bits[ (bit / CHAR_BIT) ] & (1 << (bit % CHAR_BIT))) != 0; in nsd_bitset_isset()
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
21 field bits<16> SoftFail = 0;
24 bits<2> Opcode = 0;
36 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
39 bits<5> rs1;
40 bits<5> rs2;
49 // is responsible for setting the appropriate bits in the Inst field.
50 // The bits Inst{6-2} must be set for each instruction.
51 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
54 bits<10> imm;
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H A DRISCVInstrFormatsV.td13 class RISCVVFormat<bits<3> val> {
14 bits<3> Value = val;
25 class RISCVMOP<bits<2> val> {
26 bits<2> Value = val;
38 class RISCVLSUMOP<bits<5> val> {
39 bits<5> Value = val;
49 class RISCVWidth<bits<4> val> {
50 bits<4> Value = val;
59 bits<5> uimm;
60 bits<5> rd;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td12 field bits<32> Inst;
17 bits<2> op;
18 let Inst{31-30} = op; // Top two bits are the 'op' field
26 field bits<32> SoftFail = 0;
39 bits<3> op2;
40 bits<22> imm22;
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
51 bits<5> rd;
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
61 bits<4> cond;
[all …]
/openbsd-src/lib/libm/src/
H A De_atan2l.c56 struct ieee_ext bits; in atan2l() member
63 expsigny = (uy.bits.ext_sign << 15) | uy.bits.ext_exp; in atan2l()
66 expsignx = (ux.bits.ext_sign << 15) | ux.bits.ext_exp; in atan2l()
70 ((ux.bits.ext_frach&~LDBL_NBIT) in atan2l()
72 | ux.bits.ext_frachm in atan2l()
75 | ux.bits.ext_fraclm in atan2l()
77 | ux.bits.ext_fracl)!=0) || /* x is NaN */ in atan2l()
79 ((uy.bits.ext_frach&~LDBL_NBIT) in atan2l()
81 | uy.bits.ext_frachm in atan2l()
84 | uy.bits.ext_fraclm in atan2l()
[all …]
/openbsd-src/gnu/usr.bin/perl/cpan/Compress-Raw-Zlib/zlib-src/
H A Dinffast.c29 state->bits < 8
39 - The maximum input bits used by a length/distance pair is 15 bits for the
40 length code, 5 bits for the length extra, 15 bits for the distance code,
41 and 13 bits for the distance extra. This totals 48 bits, or six bytes.
65 unsigned bits; /* local strm->bits */ in inflate_fast()
71 unsigned op; /* code bits, operatio in inflate_fast()
68 unsigned bits; /* local strm->bits */ inflate_fast() local
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/openbsd-src/sys/lib/libz/
H A Dinffast.c65 unsigned bits; /* local strm->bits */ in inflate_fast() local
92 bits = state->bits; in inflate_fast()
101 if (bits < 15) { in inflate_fast()
102 hold += (unsigned long)(*in++) << bits; in inflate_fast()
103 bits += 8; in inflate_fast()
104 hold += (unsigned long)(*in++) << bits; in inflate_fast()
105 bits += 8; in inflate_fast()
109 op = (unsigned)(here->bits); in inflate_fast()
111 bits -= op; in inflate_fast()
123 if (bits < op) { in inflate_fast()
[all …]

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