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Searched refs:X16 (Results 1 – 21 of 21) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp499 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
508 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
515 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
534 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
541 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
593 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
599 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
605 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
658 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
665 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
[all …]
H A DAArch64SLSHardening.cpp235 BuildMI(Entry, DebugLoc(), TII->get(AArch64::ORRXrs), AArch64::X16) in populateThunk()
239 BuildMI(Entry, DebugLoc(), TII->get(AArch64::BR)).addReg(AArch64::X16); in populateThunk()
295 assert(Reg != AArch64::X16 && Reg != AArch64::X17 && Reg != AArch64::LR); in ConvertBLRToBL()
H A DAArch64LowerHomogeneousPrologEpilog.cpp328 .addDef(AArch64::X16) in getOrCreateFrameHelper()
341 .addReg(Type == FrameHelperType::Epilog ? AArch64::X16 : AArch64::LR); in getOrCreateFrameHelper()
387 if (SuccMBB->isLiveIn(AArch64::W16) || SuccMBB->isLiveIn(AArch64::X16)) in shouldUseFrameHelper()
H A DAArch64ExpandPseudoInsts.cpp840 BuildMI(MBB, MBBI, DL, TII->get(Opc), AArch64::X16) in expandStoreSwiftAsyncContext()
845 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X16) in expandStoreSwiftAsyncContext()
846 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
859 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
H A DAArch64SpeculationHardening.cpp656 MisspeculatingTaintReg = AArch64::X16; in runOnMachineFunction()
H A DAArch64FrameLowering.cpp1440 BuildMI(MBB, MBBI, DL, TII->get(AArch64::LOADgot), AArch64::X16) in emitPrologue()
1445 .addUse(AArch64::X16) in emitPrologue()
1681 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead) in emitPrologue()
1693 .addReg(AArch64::X16, RegState::Define) in emitPrologue()
1704 .addReg(AArch64::X16, RegState::Kill) in emitPrologue()
1706 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead) in emitPrologue()
H A DAArch64CallingConvention.td530 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
540 (sub (sequence "X%u", 1, 28), X9, X15, X16, X17, X18, X19),
H A DAArch64RegisterInfo.cpp475 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16)) in isAsmClobberable()
H A DAArch64RegisterInfo.td120 def X16 : AArch64Reg<16, "x16", [W16]>, DwarfRegAlias<W16>;
226 def rtcGPR64 : RegisterClass<"AArch64", [i64], 64, (add X16, X17)>;
231 def GPR64noip : RegisterClass<"AArch64", [i64], 64, (sub GPR64, X16, X17, LR)>;
H A DAArch64InstrInfo.cpp7120 Reg != AArch64::X16 && // X16 is not guaranteed to be preserved. in findRegisterToSaveLRTo()
7670 Reg != AArch64::X16 && Reg != AArch64::X17 && LRU.available(Reg)) { in isMBBSafeToOutlineFrom()
H A DAArch64InstrInfo.td1356 let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
1528 let Defs = [ X9, X16, X17, NZCV ], Size = 24 in {
1533 let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in {
1540 let Uses = [ X20 ], Defs = [ X16, X17, LR, NZCV ] in {
8598 let Defs = [X16, X17], mayStore = 1, isCodeGenOnly = 1, Size = 20 in
H A DAArch64ISelLowering.cpp14924 AArch64::X16, AArch64::X17, AArch64::LR, 0 in getScratchRegisters()
/openbsd-src/sys/arch/sparc64/fpu/
H A Dfpu.c144 #define X16(x) X8(x),X8(x) macro
151 X16(FSR_NV)
158 X16(FPE_FLTOPERR_TRAP)
166 X16(FPE_FLTINV)
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h47 case AArch64::X16: return AArch64::W16; in getWRegFromXReg()
87 case AArch64::W16: return AArch64::X16; in getXRegFromWReg()
119 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16; in getXRegFromXRegTuple()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp120 {codeview::RegisterId::ARM64_X16, AArch64::X16}, in initLLVMToCVRegMapping()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td298 def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
H A DPPCFrameLowering.cpp157 {PPC::X16, -128}, \ in getCalleeSavedSpillSlots()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp898 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, in determineCalleeSaves()
H A DRISCVRegisterInfo.td100 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
H A DRISCVISelLowering.cpp11899 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
12449 RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28, in CC_RISCV_FastCC()
13551 .Case("{a6}", RISCV::X16) in getRegForInlineAsmConstraint()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1306 if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31) in matchRegisterNameHelper()