| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULibFunc.cpp | 389 P.ArgType = AMDGPULibFunc::I32; P.VectorSize = 4; break; in getNextParam()
391 P.ArgType = AMDGPULibFunc::U32; P.VectorSize = 4; break; in getNextParam()
393 P.ArgType = AMDGPULibFunc::F32; P.VectorSize = 4; break; in getNextParam()
412 P.VectorSize = 2; P.PtrKind = AMDGPULibFunc::BYVALUE; break; in getNextParam()
414 P.VectorSize = 3; P.PtrKind = AMDGPULibFunc::BYVALUE; break; in getNextParam()
416 P.VectorSize = 4; P.PtrKind = AMDGPULibFunc::BYVALUE; break; in getNextParam()
418 P.VectorSize = 8; P.PtrKind = AMDGPULibFunc::BYVALUE; break; in getNextParam()
420 P.VectorSize = 16; P.PtrKind = AMDGPULibFunc::BYVALUE; break; in getNextParam()
437 case AMDGPULibFunc::IMG1DA: P.VectorSize = 2; break; in getNextParam()
438 case AMDGPULibFunc::IMG1DB: P.VectorSize = 1; break; in getNextParam()
[all …]
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| H A D | AMDGPULibFunc.h | 294 unsigned char VectorSize; member
301 VectorSize = 1; in reset()
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| H A D | AMDGPULibCalls.cpp | 427 return FInfo.getLeads()[0].VectorSize; in getVecSize()
476 nf.getLeads()[0].VectorSize = FInfo.getLeads()[0].VectorSize; in sincosUseNative()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 247 unsigned VectorSize, MCContext &Ctx) { in ScaleVectorOffset() argument
258 auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx); in ScaleVectorOffset()
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction() local
640 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); in HexagonProcessInstruction()
650 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); in HexagonProcessInstruction()
658 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); in HexagonProcessInstruction()
666 MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext); in HexagonProcessInstruction()
681 MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext); in HexagonProcessInstruction()
696 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); in HexagonProcessInstruction()
713 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); in HexagonProcessInstruction()
[all …]
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| H A D | HexagonInstrInfo.cpp | 2777 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); in isValidOffset() local
2778 assert(isPowerOf2_32(VectorSize)); in isValidOffset()
2779 if (Offset & (VectorSize-1)) in isValidOffset()
2781 return isInt<4>(Offset >> Log2_32(VectorSize)); in isValidOffset()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 442 int VectorSize = VT.getSizeInBits(); in createShuffleStride() local
444 int LaneCount = std::max(VectorSize / 128, 1); in createShuffleStride()
455 int VectorSize = VT.getSizeInBits(); in setGroupSize() local
456 int VF = VT.getVectorNumElements() / std::max(VectorSize / 128, 1); in setGroupSize()
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| /openbsd-src/gnu/llvm/clang/lib/CodeGen/ |
| H A D | ABIInfo.h | 135 virtual bool isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
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| H A D | TargetInfo.cpp | 160 bool SwiftABIInfo::isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy, in isLegalVectorType() argument
164 return (VectorSize.getQuantity() > 8 && VectorSize.getQuantity() <= 16); in isLegalVectorType()
5568 bool isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
5953 bool AArch64SwiftABIInfo::isLegalVectorType(CharUnits VectorSize, in isLegalVectorType() argument
5958 if (VectorSize.getQuantity() != 8 && in isLegalVectorType()
5959 (VectorSize.getQuantity() != 16 || NumElts == 1)) in isLegalVectorType()
6392 bool isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
7003 bool ARMSwiftABIInfo::isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy, in isLegalVectorType() argument
7010 if (VectorSize.getQuantity() != 8 && in isLegalVectorType()
7011 (VectorSize.getQuantity() != 16 || NumElts == 1)) in isLegalVectorType()
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| H A D | CGBuiltin.cpp | 6700 int VectorSize = 0; in LookupNeonLLVMIntrinsic() local
6702 VectorSize = 64; in LookupNeonLLVMIntrinsic()
6704 VectorSize = 128; in LookupNeonLLVMIntrinsic()
6712 Ty, VectorSize ? VectorSize / Ty->getPrimitiveSizeInBits() : 1); in LookupNeonLLVMIntrinsic()
6719 int Elts = VectorSize ? VectorSize / ArgType->getPrimitiveSizeInBits() : 1; in LookupNeonLLVMIntrinsic()
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| /openbsd-src/gnu/llvm/clang/utils/TableGen/ |
| H A D | ClangOpenCLBuiltinEmitter.cpp | 260 int VectorSize) const;
983 int VectorSize) const { in getTypeString()
1017 if (VectorSize > 1) { in getTypeString()
1018 S += std::to_string(VectorSize); in getTypeString()
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| H A D | NeonEmitter.cpp | 1604 int64_t VectorSize = cast<IntInit>(Expr->getArg(0))->getValue(); in emitDagShuffle() local
1605 VectorSize /= ElementSize; in emitDagShuffle()
1608 for (unsigned VI = 0; VI < Elts2.size(); VI += VectorSize) { in emitDagShuffle()
1609 for (int LI = VectorSize - 1; LI >= 0; --LI) { in emitDagShuffle()
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| /openbsd-src/gnu/llvm/clang/lib/Sema/ |
| H A D | SemaDeclAttr.cpp | 4660 llvm::APInt VectorSize(64, 0); in AddModeAttr() local
4669 !Str.substr(1, VectorStringLength).getAsInteger(10, VectorSize) && in AddModeAttr()
4670 VectorSize.isPowerOf2()) { in AddModeAttr()
4677 VectorSize = 0; in AddModeAttr()
4681 if (!VectorSize) in AddModeAttr()
4721 VectorSize.getBoolValue()) { in AddModeAttr()
4761 if (VectorSize.getBoolValue()) { in AddModeAttr()
4762 NewTy = Context.getVectorType(NewTy, VectorSize.getZExtValue(), in AddModeAttr()
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| H A D | TreeTransform.h | 14821 IntegerLiteral *VectorSize in RebuildExtVectorType() local
14824 return SemaRef.BuildExtVectorType(ElementType, VectorSize, AttributeLoc); in RebuildExtVectorType()
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| /openbsd-src/gnu/llvm/clang/include/clang/Basic/ |
| H A D | Attr.td | 2918 def VectorSize : TypeAttr {
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