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Searched refs:VecVT (Results 1 – 25 of 29) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1432 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
1433 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
1438 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()
1671 MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, in decomposeSubvectorInsertExtractToSubRegs() argument
1677 unsigned VecRegClassID = getRegClassIDForVecVT(VecVT); in decomposeSubvectorInsertExtractToSubRegs()
1689 VecVT = VecVT.getHalfNumVectorElementsVT(); in decomposeSubvectorInsertExtractToSubRegs()
1691 InsertExtractIdx >= VecVT.getVectorElementCount().getKnownMinValue(); in decomposeSubvectorInsertExtractToSubRegs()
1693 getSubregIndexByMVT(VecVT, IsHi)); in decomposeSubvectorInsertExtractToSubRegs()
1695 InsertExtractIdx -= VecVT.getVectorElementCount().getKnownMinValue(); in decomposeSubvectorInsertExtractToSubRegs()
1888 static MVT getMaskTypeFor(MVT VecVT) { in getMaskTypeFor() argument
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H A DRISCVISelLowering.h595 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp370 EVT VecVT = N->getValueType(0); in ExpandOp_BUILD_VECTOR() local
371 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_BUILD_VECTOR()
376 assert(OldVT == VecVT.getVectorElementType() && in ExpandOp_BUILD_VECTOR()
397 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
408 EVT VecVT = N->getValueType(0); in ExpandOp_INSERT_VECTOR_ELT() local
409 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_INSERT_VECTOR_ELT()
416 assert(OldEVT == VecVT.getVectorElementType() && in ExpandOp_INSERT_VECTOR_ELT()
439 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp1402 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
1405 unsigned VecElems = VecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1420 if (VecVT.isScalableVector() == SubVecVT.isScalableVector() && in SplitVecRes_INSERT_SUBVECTOR()
1430 Align SmallestAlign = DAG.getReducedAlign(VecVT, /*UseABI=*/false); in SplitVecRes_INSERT_SUBVECTOR()
1432 DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign); in SplitVecRes_INSERT_SUBVECTOR()
1442 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1660 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, ResNE); in UnrollVectorOp_StrictFP() local
1661 return DAG.getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp_StrictFP()
1734 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_VECTOR_ELT() local
1735 EVT EltVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_VECTOR_ELT()
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H A DDAGCombiner.cpp20514 EVT VecVT = VecOp.getValueType(); in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts() local
20515 assert(!VecVT.isScalableVector() && "Only for fixed vectors."); in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20522 assert(IndexC->getZExtValue() < VecVT.getVectorNumElements() && in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20526 unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20528 if (VecVT.getScalarType() != ScalarVT) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20562 if (!(E.NumBits > 0 && E.BitPos < VecVT.getSizeInBits() && in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20563 E.BitPos + E.NumBits <= VecVT.getSizeInBits())) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20614 if (VecVT.getSizeInBits() % NewVecEltBitWidth != 0) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20629 VecVT.getSizeInBits() / NewVecEltBitWidth); in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20658 EVT VecVT = VecOp.getValueType(); in visitEXTRACT_VECTOR_ELT() local
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H A DLegalizeDAG.cpp1401 EVT VecVT = Vec.getValueType(); in ExpandExtractFromVectorThroughStack() local
1405 StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandExtractFromVectorThroughStack()
1417 StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, in ExpandExtractFromVectorThroughStack()
1422 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in ExpandExtractFromVectorThroughStack()
1424 MachinePointerInfo(), VecVT.getVectorElementType(), in ExpandExtractFromVectorThroughStack()
1450 EVT VecVT = Vec.getValueType(); in ExpandInsertToVectorThroughStack() local
1452 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandInsertToVectorThroughStack()
1462 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in ExpandInsertToVectorThroughStack()
H A DTargetLowering.cpp841 EVT VecVT = Vec.getValueType(); in SimplifyMultipleUseDemandedBits() local
842 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && in SimplifyMultipleUseDemandedBits()
1173 EVT VecVT = Vec.getValueType(); in SimplifyDemandedBits() local
1178 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { in SimplifyDemandedBits()
9352 EVT VecVT, const SDLoc &dl, in clampDynamicVectorIndex() argument
9354 assert(!(SubEC.isScalable() && VecVT.isFixedLengthVector()) && in clampDynamicVectorIndex()
9357 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
9361 if (VecVT.isScalableVector() && !SubEC.isScalable()) { in clampDynamicVectorIndex()
9386 SDValue VecPtr, EVT VecVT, in getVectorElementPointer() argument
9389 DAG, VecPtr, VecVT, in getVectorElementPointer()
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H A DSelectionDAG.cpp3691 EVT VecVT = InVec.getValueType(); in computeKnownBits() local
3693 if (VecVT.isScalableVector()) in computeKnownBits()
3695 const unsigned EltBitWidth = VecVT.getScalarSizeInBits(); in computeKnownBits()
3696 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in computeKnownBits()
4410 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits() local
4412 if (VecVT.isScalableVector()) in ComputeNumSignBits()
4416 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in ComputeNumSignBits()
11460 EVT VecVT = EVT::getVectorVT(*getContext(), EltVT, ResNE); in UnrollVectorOp() local
11461 return getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp()
11644 std::pair<SDValue, SDValue> SelectionDAG::SplitEVL(SDValue N, EVT VecVT, in SplitEVL() argument
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H A DLegalizeFloatTypes.cpp2364 EVT VecVT = Vec->getValueType(0); in PromoteFloatRes_EXTRACT_VECTOR_ELT() local
2365 EVT EltVT = VecVT.getVectorElementType(); in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2369 switch (getTypeAction(VecVT)) { in PromoteFloatRes_EXTRACT_VECTOR_ELT()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4205 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, in getVCmpInst() argument
4210 if (VecVT.isFloatingPoint()) { in getVCmpInst()
4233 if (VecVT == MVT::v4f32) in getVCmpInst()
4235 else if (VecVT == MVT::v2f64) in getVCmpInst()
4240 if (VecVT == MVT::v4f32) in getVCmpInst()
4242 else if (VecVT == MVT::v2f64) in getVCmpInst()
4247 if (VecVT == MVT::v4f32) in getVCmpInst()
4249 else if (VecVT == MVT::v2f64) in getVCmpInst()
4277 if (VecVT == MVT::v16i8) in getVCmpInst()
4279 else if (VecVT == MVT::v8i16) in getVCmpInst()
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H A DPPCISelLowering.cpp8424 EVT VecVT = Vec.getValueType(); in widenVec() local
8425 assert(VecVT.isVector() && "Expected a vector type."); in widenVec()
8426 assert(VecVT.getSizeInBits() < 128 && "Vector is already full width."); in widenVec()
8428 EVT EltVT = VecVT.getVectorElementType(); in widenVec()
8432 unsigned NumConcat = WideNumElts / VecVT.getVectorNumElements(); in widenVec()
8435 SDValue UndefVec = DAG.getUNDEF(VecVT); in widenVec()
9029 EVT VecVT = V->getValueType(0); in haveEfficientBuildVectorPattern() local
9030 bool RightType = VecVT == MVT::v2f64 || in haveEfficientBuildVectorPattern()
9031 (HasP8Vector && VecVT == MVT::v4f32) || in haveEfficientBuildVectorPattern()
9032 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); in haveEfficientBuildVectorPattern()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp745 VecVT = MVT::getVectorVT(MVT::getIntegerVT(8), 16); in isVectorConstantLegal()
758 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), in isVectorConstantLegal()
771 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), in isVectorConstantLegal()
5538 EVT VecVT = Op0.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
5543 unsigned Mask = VecVT.getVectorNumElements() - 1; in lowerEXTRACT_VECTOR_ELT()
5550 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
6052 EVT VecVT, SDValue Op, in combineExtract() argument
6059 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize(); in combineExtract()
6145 if (Op.getValueType() != VecVT) { in combineExtract()
6146 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op); in combineExtract()
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H A DSystemZISelLowering.h691 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
778 MVT VecVT; member
H A DSystemZISelDAGToDAG.cpp1162 assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); in loadVectorConstant()
1168 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); in loadVectorConstant()
1170 if (VCI.VecVT == VT.getSimpleVT()) in loadVectorConstant()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4043 MVT VecVT = MVT::Other; in forwardMustTailParameters() local
4048 VecVT = MVT::v16f32; in forwardMustTailParameters()
4050 VecVT = MVT::v8f32; in forwardMustTailParameters()
4052 VecVT = MVT::v4f32; in forwardMustTailParameters()
4058 if (VecVT != MVT::Other) in forwardMustTailParameters()
4059 RegParmTypes.push_back(VecVT); in forwardMustTailParameters()
5923 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
5924 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
5929 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()
9501 MVT VecVT = MVT::getVectorVT(VecSVT, VT.getSizeInBits() / LoadSizeInBits); in EltsFromConsecutiveLoads() local
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H A DX86ISelDAGToDAG.cpp423 MVT VecVT = N->getOperand(0).getSimpleValueType(); in getExtractVEXTRACTImmediate() local
424 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getExtractVEXTRACTImmediate()
431 MVT VecVT = N->getSimpleValueType(0); in getInsertVINSERTImmediate() local
432 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getInsertVINSERTImmediate()
439 MVT VecVT = N->getSimpleValueType(0); in getPermuteVINSERTCommutedImmediate() local
440 uint64_t InsertIdx = (Index * VecVT.getScalarSizeInBits()) / VecWidth; in getPermuteVINSERTCommutedImmediate()
1194 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 in PreprocessISelDAG() local
1199 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1201 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1206 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5717 EVT VecVT = Vec.getValueType(); in lowerINSERT_SUBVECTOR() local
5719 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_SUBVECTOR()
5727 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt, in lowerINSERT_SUBVECTOR()
5738 EVT VecVT = Vec.getValueType(); in lowerINSERT_VECTOR_ELT() local
5739 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_VECTOR_ELT()
5740 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT()
5745 unsigned NumElts = VecVT.getVectorNumElements(); in lowerINSERT_VECTOR_ELT()
5771 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat); in lowerINSERT_VECTOR_ELT()
5796 DAG.getSplatBuildVector(VecVT, SL, InsVal)); in lowerINSERT_VECTOR_ELT()
5809 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI); in lowerINSERT_VECTOR_ELT()
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H A DAMDGPUISelLowering.h199 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
H A DR600ISelLowering.cpp626 EVT VecVT = Vector.getValueType(); in vectorToVerticalVector() local
627 EVT EltVT = VecVT.getVectorElementType(); in vectorToVerticalVector()
630 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) { in vectorToVerticalVector()
635 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6206 EVT VecVT = EVT::getVectorVT( in CombineVMOVDRRCandidateWithVecOp() local
6209 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); in CombineVMOVDRRCandidateWithVecOp()
8022 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), IVT, NumElts); in LowerBUILD_VECTOR() local
8023 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops); in LowerBUILD_VECTOR()
8079 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerBUILD_VECTOR() local
8083 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
8932 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerVECTOR_SHUFFLE() local
8933 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
8934 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
8945 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerVECTOR_SHUFFLE()
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H A DARMISelDAGToDAG.cpp4310 EVT VecVT = N->getValueType(0); in Select() local
4311 EVT EltVT = VecVT.getVectorElementType(); in Select()
4312 unsigned NumElts = VecVT.getVectorNumElements(); in Select()
4316 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4322 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4327 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1), in Select()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3113 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { in aggressivelyPreferBuildVectorSources() argument
5033 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
5041 SDValue getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp397 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
398 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
403 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp8553 EVT VecVT; in LowerFCOPYSIGN() local
8557 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
8559 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
8561 VecVal1 = BitCast(VecVT, In1, DAG); in LowerFCOPYSIGN()
8562 VecVal2 = BitCast(VecVT, In2, DAG); in LowerFCOPYSIGN()
8566 VecVT = IntVT; in LowerFCOPYSIGN()
8569 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
8572 VecVT = MVT::v4i32; in LowerFCOPYSIGN()
8575 VecVT = MVT::v8i16; in LowerFCOPYSIGN()
8582 SDValue SignMaskV = DAG.getConstant(~APInt::getSignMask(BitWidth), DL, VecVT); in LowerFCOPYSIGN()
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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVEISelLowering.cpp92 for (MVT VecVT : AllVectorVTs) in initRegisterClasses() local
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()

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