| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 49 unsigned ValueReg, unsigned Address,
55 unsigned ValueReg, unsigned Address,
245 unsigned ValueReg, unsigned Address,
253 unsigned ValueReg, unsigned Address,
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| H A D | R600InstrInfo.cpp | 1089 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1091 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1096 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1112 AddrReg, ValueReg) in buildIndirectWrite()
1121 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1123 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1128 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1144 ValueReg, in buildIndirectRead()
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| H A D | SIRegisterInfo.cpp | 1193 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1207 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1208 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1211 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1308 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1326 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1520 ? ValueReg in buildSpillLoadStore()
1521 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1554 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1555 : ValueReg; in buildSpillLoadStore()
[all …]
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| H A D | SIRegisterInfo.h | 409 unsigned LoadStoreOp, int Index, Register ValueReg,
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 1288 Register ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1289 if (ValueReg == 0) in selectStore()
1292 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1298 MIB.addReg(ValueReg); in selectStore()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
191 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
221 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVBuiltins.cpp | 1448 Register ValueReg = BitcastMI->getOperand(2).getReg(); in getBlockStructInstr() local
1449 MachineInstr *ValueMI = MRI->getUniqueVRegDef(ValueReg); in getBlockStructInstr()
1472 Register ValueReg = MI->getOperand(0).getReg(); in getMachineInstrType() local
1474 NextMI->getOperand(1).getReg() != ValueReg) in getMachineInstrType()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11728 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
11729 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
11731 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
11874 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
11877 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11878 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
11883 .addReg(ValueReg); in EmitPartwordAtomicBinary()
11884 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
11887 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ValueReg).addReg(CmpReg); in EmitPartwordAtomicBinary()
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