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Searched refs:VT (Results 1 – 25 of 338) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp171 EVT VT = N->getValueType(0); in SelectExtractHigh() local
174 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
175 Index != VT.getVectorNumElements()) in SelectExtractHigh()
185 EVT VT = Op.getValueType(); in SelectRoundingVLShr() local
187 if (ShtAmt > VT.getScalarSizeInBits() / 2 || Op.getOpcode() != ISD::ADD) in SelectRoundingVLShr()
192 Imm = APInt(VT.getScalarSizeInBits(), in SelectRoundingVLShr()
197 Imm = APInt(VT.getScalarSizeInBits(), in SelectRoundingVLShr()
246 template<MVT::SimpleValueType VT>
248 return SelectSVEAddSubImm(N, VT, Imm, Shift); in SelectSVEAddSubImm()
251 template <MVT::SimpleValueType VT>
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H A DAArch64ISelLowering.cpp143 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT() argument
144 switch (VT.getSimpleVT().SimpleTy) { in getPackedSVEVectorVT()
183 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate() argument
184 assert(VT.isScalableVector() && (VT.getVectorElementType() == MVT::i1) && in getPromotedVTForPredicate()
186 switch (VT.getVectorMinNumElements()) { in getPromotedVTForPredicate()
205 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
206 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in isPackedVectorType()
208 return VT.isFixedLengthVector() || in isPackedVectorType()
209 VT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock; in isPackedVectorType()
396 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
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H A DAArch64FastISel.cpp183 bool isTypeLegal(Type *Ty, MVT &VT);
184 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
188 bool simplifyAddress(Address &Addr, MVT VT);
226 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
228 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
230 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
237 unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
266 unsigned materializeInt(const ConstantInt *CI, MVT VT);
267 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
318 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.h44 bool operator==(EVT VT) const {
45 return !(*this != VT);
47 bool operator!=(EVT VT) const {
48 if (V.SimpleTy != VT.V.SimpleTy)
51 return LLVMTy != VT.LLVMTy;
73 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
75 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
78 return getExtendedVectorVT(Context, VT, NumElements, IsScalable);
83 static EVT getVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getVectorVT()
84 MVT M = MVT::getVectorVT(VT.V, EC); in getVectorVT()
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H A DTargetLowering.h443 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask() argument
465 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction() argument
467 if (VT.getVectorElementCount().isScalar()) in getPreferredVectorAction()
470 if (!VT.isPow2VectorType()) in getPreferredVectorAction()
501 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap() argument
504 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem() argument
525 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
531 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
537 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
543 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
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H A DSelectionDAG.h108 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
109 FastID(ID), VTs(VT), NumVTs(Num) {
636 SDVTList getVTList(EVT VT);
651 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
653 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
656 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
658 return getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT,
662 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
666 SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
671 SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp204 EVT VT = getOptimalMemOpType(Op, FuncAttributes); in findOptimalMemOpLowering() local
206 if (VT == MVT::Other) { in findOptimalMemOpLowering()
210 VT = MVT::i64; in findOptimalMemOpLowering()
212 while (Op.getDstAlign() < (VT.getSizeInBits() / 8) && in findOptimalMemOpLowering()
213 !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign())) in findOptimalMemOpLowering()
214 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
215 assert(VT.isInteger()); in findOptimalMemOpLowering()
225 if (VT.bitsGT(LVT)) in findOptimalMemOpLowering()
226 VT = LVT; in findOptimalMemOpLowering()
232 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering()
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H A DDAGCombiner.cpp251 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
252 if (EVT(VT).isSimple() && VT != MVT::Other && in DAGCombiner()
253 TLI.isTypeLegal(EVT(VT)) && in DAGCombiner()
254 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits) in DAGCombiner()
255 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue(); in DAGCombiner()
390 SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
571 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
581 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
784 bool hasOperation(unsigned Opcode, EVT VT) { in hasOperation() argument
785 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations); in hasOperation()
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H A DSelectionDAG.cpp124 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
126 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
131 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), in isValueValidForType()
1076 EVT VT = N->getValueType(0); in VerifySDNode() local
1078 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
1083 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in VerifySDNode()
1085 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
1152 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1153 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
1154 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
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H A DLegalizeVectorOps.cpp573 MVT VT = Node->getSimpleValueType(0); in Promote() local
574 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in Promote()
595 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
596 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
598 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, in Promote()
601 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
611 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
612 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in PromoteINT_TO_FP()
613 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() && in PromoteINT_TO_FP()
649 MVT VT = Node->getSimpleValueType(0); in PromoteFP_TO_INT() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp22 LLVMContext &Context, CallingConv::ID CC, EVT VT) const { in getNumRegistersForCallingConv()
26 if (VT.isVector() && VT.getVectorNumElements() == 3 && in getNumRegistersForCallingConv()
27 (VT.getVectorElementType() == MVT::i1 || in getNumRegistersForCallingConv()
28 VT.getVectorElementType() == MVT::i8)) in getNumRegistersForCallingConv()
30 return getNumRegisters(Context, VT); in getNumRegistersForCallingConv()
35 EVT VT) const { in getRegisterTypeForCallingConv()
39 if (VT.isVector() && VT.getVectorNumElements() == 3) { in getRegisterTypeForCallingConv()
40 if (VT.getVectorElementType() == MVT::i1) in getRegisterTypeForCallingConv()
42 else if (VT.getVectorElementType() == MVT::i8) in getRegisterTypeForCallingConv()
45 return getRegisterType(Context, VT); in getRegisterTypeForCallingConv()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp184 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
185 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
198 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) { in X86TargetLowering()
199 setCondCodeAction(ISD::SETOEQ, VT, Expand); in X86TargetLowering()
200 setCondCodeAction(ISD::SETUNE, VT, Expand); in X86TargetLowering()
303 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) { in X86TargetLowering()
304 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in X86TargetLowering()
305 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
339 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
340 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
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H A DX86InterleavedAccess.cpp233 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
234 unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2; in scaleVectorType()
236 VT.getVectorNumElements() / 2); in scaleVectorType()
261 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland() argument
264 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
266 unsigned NumOfElm = VT.getVectorNumElements(); in genShuffleBland()
291 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector() argument
306 genShuffleBland(VT, VPShuf, OptimizeShuf, (i / Stride) * 16, in reorderSubVector()
331 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
342 createUnpackShuffleMask(VT, MaskLowTemp1, true, false); in interleave8bitStride4VF8()
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H A DX86ISelLowering.h978 MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override { in getScalarShiftAmountTy() argument
1010 bool isSafeMemOpType(MVT VT) const override;
1012 bool isMemoryAccessFast(EVT VT, Align Alignment) const;
1016 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
1025 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1030 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1033 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), in allowsMemoryAccess()
1053 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
1091 bool hasBitPreservingFPLogic(EVT VT) const override;
1136 auto VTIsOk = [](EVT VT) -> bool { in shouldTransformSignedTruncationCheck()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DCallingConvLower.cpp87 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
100 MVT VT = Outs[i].VT; in CheckReturn() local
102 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
114 MVT VT = Outs[i].VT; in AnalyzeReturn() local
116 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeReturn()
127 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
162 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
164 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
167 << EVT(VT).getEVTString() << '\n'; in AnalyzeCallResult()
175 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult() argument
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H A DTargetLoweringBase.cpp216 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
223 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
224 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
225 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
226 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
227 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
502 MVT VT) { in getOUTLINE_ATOMIC() argument
504 switch (VT.SimpleTy) { in getOUTLINE_ATOMIC()
578 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
581 switch (VT.SimpleTy) { \ in getSYNC()
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp74 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
76 VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL; in PreprocessISelDAG()
79 Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
88 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
93 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && in PreprocessISelDAG()
119 SDVTList VTs = CurDAG->getVTList({VT, MVT::Other}); in PreprocessISelDAG()
175 static SDNode *selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, in selectImmSeq() argument
178 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT); in selectImmSeq()
180 SDValue SDImm = CurDAG->getTargetConstant(Inst.getImm(), DL, VT); in selectImmSeq()
183 Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, VT, SDImm); in selectImmSeq()
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H A DRISCVISelLowering.cpp134 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering() argument
138 if (VT.getVectorMinNumElements() < MinElts) in RISCVTargetLowering()
141 unsigned Size = VT.getSizeInBits().getKnownMinValue(); in RISCVTargetLowering()
154 addRegisterClass(VT, RC); in RISCVTargetLowering()
157 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
158 addRegClassForRVV(VT); in RISCVTargetLowering()
159 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
160 if (VT.getVectorElementType() == MVT::i64 && in RISCVTargetLowering()
163 addRegClassForRVV(VT); in RISCVTargetLowering()
167 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp62 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
64 setLoadExtAction(N, VT, MVT::i1, Promote); in AVRTargetLowering()
65 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
71 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
72 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
73 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
74 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
75 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
140 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
141 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp39 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
40 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
143 for (MVT VT : MVT::integer_valuetypes()) in AMDGPUTargetLowering() local
144 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT, in AMDGPUTargetLowering()
147 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
148 if (VT == MVT::i64) in AMDGPUTargetLowering()
152 setLoadExtAction(Op, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
153 setLoadExtAction(Op, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
154 setLoadExtAction(Op, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
155 setLoadExtAction(Op, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp159 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) { in addTypeForNEON() argument
160 if (VT != PromotedLdStVT) { in addTypeForNEON()
161 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
162 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
164 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
165 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
168 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
170 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
171 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
172 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
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/openbsd-src/gnu/llvm/llvm/lib/Support/
H A DLowLevelType.cpp18 LLT::LLT(MVT VT) { in LLT() argument
19 if (VT.isVector()) { in LLT()
20 bool asVector = VT.getVectorMinNumElements() > 1; in LLT()
22 VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(), in LLT()
24 } else if (VT.isValid()) { in LLT()
28 ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp48 for (EVT VT : VTs) { in computeLegalValueVTs() local
49 unsigned NumRegs = TLI.getNumRegisters(Ctx, VT); in computeLegalValueVTs()
50 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs()
126 for (auto VT : MFI.getParams()) in WebAssemblyFunctionInfo() local
127 Params.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo()
128 for (auto VT : MFI.getResults()) in WebAssemblyFunctionInfo() local
129 Results.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo()
157 for (auto VT : YamlMFI.Params) in initializeBaseYamlFields() local
158 addParam(WebAssembly::parseMVT(VT.Value)); in initializeBaseYamlFields()
159 for (auto VT : YamlMFI.Results) in initializeBaseYamlFields() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp84 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) { in BPFTargetLowering()
85 if (VT == MVT::i32) { in BPFTargetLowering()
89 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom); in BPFTargetLowering()
92 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom); in BPFTargetLowering()
93 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom); in BPFTargetLowering()
94 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom); in BPFTargetLowering()
95 setOperationAction(ISD::ATOMIC_SWAP, VT, Custom); in BPFTargetLowering()
96 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom); in BPFTargetLowering()
99 for (auto VT : { MVT::i32, MVT::i64 }) { in BPFTargetLowering()
100 if (VT == MVT::i32 && !STI.getHasAlu32()) in BPFTargetLowering()
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/openbsd-src/gnu/llvm/llvm/include/llvm/Support/
H A DVersionTuple.h173 friend hash_code hash_value(const VersionTuple &VT) { in hash_value() argument
174 return hash_combine(VT.Major, VT.Minor, VT.Subminor, VT.Build); in hash_value()
179 const VersionTuple &VT) { in addHash() argument
180 HBuilder.add(VT.Major, VT.Minor, VT.Subminor, VT.Build); in addHash()

12345678910>>...14