Home
last modified time | relevance | path

Searched refs:VSCALE (Results 1 – 11 of 11) sorted by relevance

/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1253 VSCALE, enumerator
H A DSelectionDAG.h1065 return getNode(ISD::VSCALE, DL, VT,
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp178 case ISD::VSCALE: return "vscale"; in getOperationName()
H A DSelectionDAG.cpp3971 if (Val.getOpcode() == ISD::VSCALE && in isKnownToBeAPowerOfTwo()
5509 if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes) in getNode()
5582 case ISD::VSCALE: in getNode()
6191 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
6259 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
H A DDAGCombiner.cpp2673 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2681 N0.getOperand(1).getOpcode() == ISD::VSCALE && in visitADD()
2682 N1.getOpcode() == ISD::VSCALE) { in visitADD()
3746 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { in visitSUB()
4177 if (N0.getOpcode() == ISD::VSCALE && NC1) { in visitMUL()
9385 if (N0.getOpcode() == ISD::VSCALE && N1C) { in visitSHL()
H A DLegalizeIntegerTypes.cpp106 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
2570 case ISD::VSCALE: in ExpandIntegerResult()
H A DSelectionDAGBuilder.cpp4000 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp471 setOperationAction(ISD::VSCALE, XLenVT, Custom); in RISCVTargetLowering()
3855 case ISD::VSCALE: { in LowerOperation()
6292 SlideupAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlideupAmt); in lowerINSERT_SUBVECTOR()
6298 VL = DAG.getNode(ISD::VSCALE, DL, XLenVT, VL); in lowerINSERT_SUBVECTOR()
6425 SlidedownAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlidedownAmt); in lowerEXTRACT_SUBVECTOR()
6527 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVECTOR_REVERSE()
6559 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVECTOR_SPLICE()
12669 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerFormalArguments()
12963 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerCall()
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td345 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp5846 if (VScale.getOpcode() != ISD::VSCALE) in SelectAddrModeIndexedSVE()
H A DAArch64ISelLowering.cpp1534 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
6011 case ISD::VSCALE: in LowerOperation()
16531 if (VS.getOpcode() != ISD::VSCALE) in performLastTrueTestVectorCombine()