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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 30) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1219 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1220 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1221 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1222 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1223 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1224 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1226 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1227 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1228 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1229 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; in getShuffleCost()
[all …]
H A DARMISelLowering.cpp185 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
252 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
400 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
442 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
1014 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
10461 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
18406 N->getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE && in PerformMVETruncCombine()
18407 N->getOperand(1).getOpcode() == ISD::VECTOR_SHUFFLE) { in PerformMVETruncCombine()
18436 Op.getOpcode() == ISD::VECTOR_SHUFFLE || in PerformMVETruncCombine()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h586 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1537 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1582 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
156 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); in initializeHVXLowering()
157 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); in initializeHVXLowering()
158 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); in initializeHVXLowering()
159 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); in initializeHVXLowering()
248 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
312 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
3532 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
3534 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
H A DHexagonISelLowering.cpp1645 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1750 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1751 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1752 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3342 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2794 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2804 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2806 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
H A DHexagonISelDAGToDAG.cpp927 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVECustomDAG.cpp255 case ISD::VECTOR_SHUFFLE: in getIdiomaticVectorType()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp161 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
195 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
1428 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2665 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp301 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp1803 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
5443 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { in hoistLogicOpWithSameOpcodeHands()
14379 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
20331 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
20778 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
20812 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
21227 !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
21260 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
21410 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT)) in reduceBuildVecToShuffle()
21618 bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
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H A DSelectionDAG.cpp875 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
2087 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2662 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2820 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
3015 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
4057 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
6678 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp70 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
997 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
3916 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
H A DLegalizeDAG.cpp3063 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
4680 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
H A DTargetLowering.cpp870 case ISD::VECTOR_SHUFFLE: { in SimplifyMultipleUseDemandedBits()
1297 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedBits()
3205 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedVectorElts()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp356 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
654 ISD::VECTOR_SHUFFLE, in SystemZTargetLowering()
4938 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
5791 case ISD::VECTOR_SHUFFLE: in LowerOperation()
6066 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
6428 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
7138 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
811 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
1039 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1087 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1382 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
11358 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
15028 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
15029 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
15222 if (UI.getUse().getResNo() == 0 && UI->getOpcode() != ISD::VECTOR_SHUFFLE) in combineVReverseMemOP()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1856 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp344 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
460 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td322 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp988 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); in X86TargetLowering()
1092 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1099 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1535 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1644 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1878 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2006 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2071 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2198 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2211 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32bf16, Custom); in X86TargetLowering()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp436 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
453 ISD::VSELECT, ISD::SELECT_CC, ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td700 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1579 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
1800 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForStreamingSVE()
1928 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForFixedLengthSVE()
5911 case ISD::VECTOR_SHUFFLE: in LowerOperation()
15437 BV.getOpcode() != ISD::VECTOR_SHUFFLE) in performBuildShuffleExtendCombine()
15452 if (BV.getOpcode() == ISD::VECTOR_SHUFFLE && in performBuildShuffleExtendCombine()

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