Searched refs:UZP2 (Results 1 – 7 of 7) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 200 UZP2, enumerator
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| H A D | AArch64SchedKryoDetails.td | 2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>; 2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>; 2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
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| H A D | AArch64SchedFalkorDetails.td | 920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
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| H A D | AArch64SchedThunderX3T110.td | 1643 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
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| H A D | AArch64ISelLowering.cpp | 2382 MAKE_CASE(AArch64ISD::UZP2) in getTargetNodeName() 5027 return DAG.getNode(AArch64ISD::UZP2, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN() 11152 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle() 11562 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE() 11575 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE() 12334 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), LHS, in LowerBUILD_VECTOR() 23817 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerFixedLengthVECTOR_SHUFFLEToSVE() 23827 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerFixedLengthVECTOR_SHUFFLEToSVE()
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| H A D | AArch64SchedA64FX.td | 1696 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
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| H A D | AArch64InstrInfo.td | 648 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>; 5483 // Prioritize ADDHN and SUBHN over UZP2. 5590 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
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