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Searched refs:UZP1 (Results 1 – 7 of 7) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h199 UZP1, enumerator
H A DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
H A DAArch64ISelLowering.cpp2381 MAKE_CASE(AArch64ISD::UZP1) in getTargetNodeName()
5024 return DAG.getNode(AArch64ISD::UZP1, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
11149 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
11562 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
11575 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
12331 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS, in LowerBUILD_VECTOR()
12725 return DAG.getNode(AArch64ISD::UZP1, DL, VT, NewLo, Hi); in LowerINSERT_SUBVECTOR()
12730 return DAG.getNode(AArch64ISD::UZP1, DL, VT, Lo, NewHi); in LowerINSERT_SUBVECTOR()
12759 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, Vec1, HiVec0); in LowerINSERT_SUBVECTOR()
12764 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, LoVec0, Vec1); in LowerINSERT_SUBVECTOR()
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H A DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
H A DAArch64SchedThunderX3T110.td1643 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64SchedA64FX.td1696 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td647 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
5589 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;