| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 43 UXTW, enumerator
63 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
130 case 2: return AArch64_AM::UXTW; in getExtendType()
157 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
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| H A D | AArch64InstPrinter.cpp | 1262 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1268 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 20 def CheckExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
36 def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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| H A D | AArch64RegisterInfo.td | 1428 // UXTW(8|16|32|64)
1429 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1430 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
1431 def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
1432 def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
1433 def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
1435 …def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "On…
1436 def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
1437 def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
1438 def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
[all …]
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| H A D | AArch64FastISel.cpp | 753 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
777 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
835 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
872 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
892 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
1075 Addr.getExtendType() == AArch64_AM::UXTW ) in simplifyAddress()
1084 if (Addr.getExtendType() == AArch64_AM::UXTW) in simplifyAddress()
1829 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitLoad()
2119 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitStore()
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| H A D | AArch64ISelDAGToDAG.cpp | 783 return AArch64_AM::UXTW; in getExtendTypeForNode()
801 return AArch64_AM::UXTW; in getExtendTypeForNode()
1006 if (Ext == AArch64_AM::UXTW && Reg->getValueType(0).getSizeInBits() == 32 && in SelectArithExtendedRegister()
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| H A D | AArch64InstrInfo.cpp | 907 case AArch64_AM::UXTW: in isFalkorShiftExtFast()
941 case AArch64_AM::UXTW: in isFalkorShiftExtFast()
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| H A D | AArch64InstrFormats.td | 2787 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
2789 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
2894 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 617 UXTW, enumerator
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1314 if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW || in isSVEDataVectorRegWithShiftExtend()
1506 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1519 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW; in isExtend64()
1544 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
2088 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
3571 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6652 return AArch64_AM::UXTW; in getExtendTypeForInst()
6675 return AArch64_AM::UXTW; in getExtendTypeForInst()
6744 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstrMVE.td | 210 // mve_addr_rq_shift := reg + vreg{ << UXTW #shift}
6332 // [Rn,Qm,UXTW #2] or similar.
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