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Searched refs:TSFlags (Results 1 – 25 of 126) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h134 static inline unsigned getFormat(uint64_t TSFlags) { in getFormat() argument
135 return (TSFlags & InstFormatMask) >> InstFormatShift; in getFormat()
138 static inline VConstraintType getConstraint(uint64_t TSFlags) { in getConstraint() argument
139 return static_cast<VConstraintType>((TSFlags & ConstraintMask) >> in getConstraint()
143 static inline VLMUL getLMul(uint64_t TSFlags) { in getLMul() argument
144 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
147 static inline bool hasDummyMaskOp(uint64_t TSFlags) { in hasDummyMaskOp() argument
148 return TSFlags & HasDummyMaskOpMask; in hasDummyMaskOp()
151 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { in doesForceTailAgnostic() argument
152 return TSFlags & ForceTailAgnosticMask; in doesForceTailAgnostic()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h355 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
359 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
363 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
367 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
379 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
383 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
387 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
391 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
395 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
399 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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H A DSIInstrFormats.td157 let TSFlags{0} = SALU;
158 let TSFlags{1} = VALU;
160 let TSFlags{2} = SOP1;
161 let TSFlags{3} = SOP2;
162 let TSFlags{4} = SOPC;
163 let TSFlags{5} = SOPK;
164 let TSFlags{6} = SOPP;
166 let TSFlags{7} = VOP1;
167 let TSFlags{8} = VOP2;
168 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
59 let TSFlags{8-7} = FlagOperandIdx;
60 let TSFlags{9} = HasNativeOperands;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
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H A DAMDGPUInsertDelayAlu.cpp48 if (MI.getDesc().TSFlags & VA_VDST_0) in instructionWaitsForVALU()
63 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType() argument
64 if (TSFlags & SIInstrFlags::TRANS) in getDelayType()
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
68 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
348 DelayType Type = getDelayType(MI.getDesc().TSFlags); in runOnMachineBasicBlock()
H A DSIPostRABundler.cpp110 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
116 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
120 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
H A DR600Defines.h59 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
60 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
83 let TSFlags{9} = isRestrictSlot1AOK;
87 let TSFlags{10} = isPredicated;
89 let TSFlags{11} = isPredicatedFalse;
91 let TSFlags{12} = isPredicatedNew;
93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
97 let TSFlags{14} = isNewValue; // New-value consumer insn.
99 let TSFlags{15} = hasNewValue; // New-value producer insn.
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp80 uint64_t TSFlags, bool HasREX, uint64_t StartByte,
121 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8() argument
122 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
125 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isDispOrCDisp8()
144 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
145 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
146 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
148 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
200 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4) in isPCRel32Branch()
322 uint64_t TSFlags, bool HasREX, in emitMemModRMByte() argument
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H A DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
156 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
166 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
167 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
170 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { in printVecCompareInstr()
171 assert(!(Desc.TSFlags & X86II::VEX_W) && "Unknown W-bit value!"); in printVecCompareInstr()
173 } else if (Desc.TSFlags & X86II::VEX_W) { in printVecCompareInstr()
181 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86ATTInstPrinter.cpp102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
174 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
176 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
177 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
180 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { in printVecCompareInstr()
181 assert(!(Desc.TSFlags & X86II::VEX_W) && "Unknown W-bit value!"); in printVecCompareInstr()
183 } else if (Desc.TSFlags & X86II::VEX_W) { in printVecCompareInstr()
191 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86BaseInfo.h979 inline bool isPrefix(uint64_t TSFlags) { in isPrefix() argument
980 return (TSFlags & X86II::FormMask) == PrefixByte; in isPrefix()
984 inline bool isPseudo(uint64_t TSFlags) { in isPseudo() argument
985 return (TSFlags & X86II::FormMask) == Pseudo; in isPseudo()
990 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
991 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
994 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
995 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
1000 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
1001 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
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H A DX86InstPrinterCommon.cpp360 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
363 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
366 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
375 if ((Flags & X86::IP_USE_VEX) || (TSFlags & X86II::ExplicitVEXPrefix)) in printInstFlags()
390 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); in printInstFlags()
396 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { in printInstFlags()
/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td49 let TSFlags{3...0} = VecInstType;
50 let TSFlags{4...4} = IsSimpleMove;
51 let TSFlags{5...5} = IsLoad;
52 let TSFlags{6...6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9...8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp247 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
248 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
252 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
260 else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) in generateWaitCntInfo()
268 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
269 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
280 (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet))) in generateWaitCntInfo()
282 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
284 } else if (MCID.TSFlags & SIInstrFlags::EXP) { in generateWaitCntInfo()
301 return MCID.TSFlags & SIInstrFlags::MUBUF || in isVMEM()
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp141 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
144 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
148 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
149 (TSFlags & X86II::OpMapMask) == X86II::T8) || in getFMA3Group()
150 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
151 ((TSFlags & X86II::OpMapMask) == X86II::T8 || in getFMA3Group()
152 (TSFlags & X86II::OpMapMask) == X86II::T_MAP6)); in getFMA3Group()
153 bool IsFMA3Prefix = (TSFlags & X86II::OpPrefixMask) == X86II::PD; in getFMA3Group()
160 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
162 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
H A DX86EvexToVex.cpp226 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEvexToVexImpl()
232 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B)) in CompressEvexToVexImpl()
237 if (Desc.TSFlags & X86II::EVEX_L2) in CompressEvexToVexImpl()
254 (Desc.TSFlags & X86II::VEX_L) ? ArrayRef(X86EvexToVex256CompressTable) in CompressEvexToVexImpl()
H A DX86InstrFormats.td372 // TSFlags layout should be kept in sync with X86BaseInfo.h.
373 let TSFlags{6-0} = FormBits;
374 let TSFlags{8-7} = OpSizeBits;
375 let TSFlags{10-9} = AdSizeBits;
377 let TSFlags{12-11} = OpPrefixBits{1-0};
378 let TSFlags{16-13} = OpMapBits;
379 let TSFlags{17} = hasREX_W;
380 let TSFlags{21-18} = ImmT.Value;
381 let TSFlags{24-22} = FPForm.Value;
382 let TSFlags{25} = hasLockPrefix;
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp120 if (!RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in isMaskRegOp()
243 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded() local
244 if (RISCVII::hasSEWOp(TSFlags)) { in getDemanded()
246 if (RISCVII::hasVLOp(TSFlags)) in getDemanded()
250 if (!RISCVII::usesMaskPolicy(TSFlags)) in getDemanded()
266 if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) { in getDemanded()
635 static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, in INITIALIZE_PASS()
647 if (RISCVII::hasVecPolicyOp(TSFlags)) { in INITIALIZE_PASS()
666 if (RISCVII::doesForceTailAgnostic(TSFlags)) in INITIALIZE_PASS()
669 if (!RISCVII::usesMaskPolicy(TSFlags)) in INITIALIZE_PASS()
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H A DRISCVMCInstLower.cpp154 uint64_t TSFlags = MI->getDesc().TSFlags; in lowerRISCVVMachineInstrToMCInst() local
158 if (RISCVII::hasVecPolicyOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
160 if (RISCVII::hasVLOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
162 if (RISCVII::hasSEWOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
173 if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) { in lowerRISCVVMachineInstrToMCInst()
210 if (RISCVII::hasDummyMaskOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
H A DRISCVInstrFormats.td175 let TSFlags{4-0} = format.Value;
179 let TSFlags{7-5} = RVVConstraint.Value;
182 let TSFlags{10-8} = VLMul;
185 let TSFlags{11} = HasDummyMask;
188 let TSFlags{12} = ForceTailAgnostic;
191 let TSFlags{13} = HasMergeOp;
194 let TSFlags{14} = HasSEWOp;
197 let TSFlags{15} = HasVLOp;
200 let TSFlags{16} = HasVecPolicyOp;
203 let TSFlags{17} = IsRVVWideningReduction;
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
425 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
515 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp32 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
53 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
63 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
113 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in getBaseOffset()
115 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in getBaseOffset()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp134 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
135 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
161 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()

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