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Searched refs:SubReg (Results 1 – 25 of 79) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DLiveVariables.cpp195 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
196 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
201 LastDefReg = SubReg; in FindLastPartialDef()
249 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
250 if (Processed.count(SubReg)) in HandlePhysRegUse()
252 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
256 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
259 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
260 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
288 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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H A DLiveIntervalCalc.cpp59 unsigned SubReg = MO.getSubReg(); in calculate() local
60 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
61 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
159 unsigned SubReg = MO.getSubReg(); in extendToUses() local
160 if (SubReg != 0) { in extendToUses()
161 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DPeepholeOptimizer.cpp296 ValueTrackerResult(Register Reg, unsigned SubReg) { in ValueTrackerResult() argument
297 addSource(Reg, SubReg); in ValueTrackerResult()
332 return RegSrcs[Idx].SubReg; in getSrcSubReg()
701 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
751 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
752 CurSrcPair.SubReg)) in findNextSource()
757 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
783 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
791 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1073 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
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H A DDetectDeadLanes.cpp171 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
172 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
421 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
444 if (SubReg == 0) in determineInitialUsedLanes()
447 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
454 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
455 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
H A DLiveIntervals.cpp564 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
565 if (SubReg != 0) { in shrinkToUses()
566 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
783 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
784 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1025 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1026 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1042 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1043 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1457 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
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H A DLiveRangeEdit.cpp140 unsigned SubReg = MO.getSubReg(); in allUsesAvailableAt() local
141 LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in allUsesAvailableAt()
275 unsigned SubReg = MO.getSubReg(); in useIsKill() local
276 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
H A DMachineInstrBundle.cpp203 unsigned SubReg = *SubRegs; in finalizeBundle() local
204 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
205 LocalDefs.push_back(SubReg); in finalizeBundle()
H A DScheduleDAGInstrs.cpp337 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) { in addPhysRegDeps() local
338 if (Uses.contains(*SubReg)) in addPhysRegDeps()
339 Uses.eraseAll(*SubReg); in addPhysRegDeps()
341 Defs.eraseAll(*SubReg); in addPhysRegDeps()
373 unsigned SubReg = MO.getSubReg(); in getLaneMaskForMO() local
374 if (SubReg == 0) in getLaneMaskForMO()
376 return TRI->getSubRegIndexLaneMask(SubReg); in getLaneMaskForMO()
H A DLiveDebugVariables.cpp542 unsigned SubReg; /// Qualifiying subregister for Reg. member
1281 unsigned SubReg = Position.SubReg; in runOnMachineFunction() local
1283 PHIValPos VP = {SI, Reg, SubReg}; in runOnMachineFunction()
1838 unsigned SubReg = It.second.SubReg; in emitDebugValues() local
1844 if (SubReg != 0) in emitDebugValues()
1845 PhysReg = TRI->getSubReg(PhysReg, SubReg); in emitDebugValues()
1857 if (SubReg) in emitDebugValues()
1858 regSizeInBits = TRI->getSubRegIdxSize(SubReg); in emitDebugValues()
1864 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
1879 dbgs() << "DBG_PHI for Vreg " << Reg << " subreg " << SubReg << in emitDebugValues()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
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H A DAArch64RegisterInfo.cpp312 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), in UpdateCustomCallPreservedMask() local
314 SubReg.isValid(); ++SubReg) { in UpdateCustomCallPreservedMask()
317 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32); in UpdateCustomCallPreservedMask()
422 for (MCSubRegIterator SubReg(AArch64::ZA, this, /*self=*/true); in getStrictlyReservedRegs() local
423 SubReg.isValid(); ++SubReg) in getStrictlyReservedRegs()
424 Reserved.set(*SubReg); in getStrictlyReservedRegs()
970 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp257 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
258 CodeGenRegister *SR = SubReg.second; in inheritRegUnits()
351 for (const auto &SubReg : Map) in computeSubRegs() local
352 if (Orphans.erase(SubReg.second)) in computeSubRegs()
353 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
357 for (const auto &SubReg : SubRegs) { in computeSubRegs() local
358 if (SubReg.second == this) { in computeSubRegs()
368 SubReg.first->AllSuperRegsCovered = false; in computeSubRegs()
372 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
373 if (Ins->second == SubReg.first) in computeSubRegs()
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/openbsd-src/gnu/llvm/llvm/lib/MC/
H A DMCRegisterInfo.cpp45 MCRegister SubReg) const { in getSubRegIndex()
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
51 if (*Subs == SubReg) in getSubRegIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h298 unsigned SubReg,
347 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
369 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg() argument
370 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getChannelFromSubReg()
374 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg() argument
375 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
H A DSIShrinkInstructions.cpp56 Register Reg, unsigned SubReg) const;
58 unsigned SubReg) const;
60 unsigned SubReg) const;
555 unsigned SubReg) const { in instAccessReg()
564 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubReg) & in instAccessReg()
574 unsigned SubReg) const { in instReadsReg()
575 return instAccessReg(MI->uses(), Reg, SubReg); in instReadsReg()
579 unsigned SubReg) const { in instModifiesReg()
580 return instAccessReg(MI->defs(), Reg, SubReg); in instModifiesReg()
716 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
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H A DSIPreAllocateWWMRegs.cpp131 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
132 if (SubReg != 0) { in rewriteRegs()
133 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
H A DSIRegisterInfo.cpp1519 Register SubReg = e == 1 in buildSpillLoadStore() local
1582 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1588 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1601 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
1606 SubReg = TmpIntermediateVGPR; in buildSpillLoadStore()
1622 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
1725 Register SubReg = in spillSGPR() local
1740 .addReg(SubReg, getKillRegState(UseKill)) in spillSGPR()
1779 Register SubReg = in spillSGPR() local
1787 .addReg(SubReg, SubKillState) in spillSGPR()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h496 unsigned SubReg; member
498 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
499 : Reg(Reg), SubReg(SubReg) {} in Reg()
502 return Reg == P.Reg && SubReg == P.SubReg;
515 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
517 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
2096 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2103 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
H A DMachineInstrBuilder.h98 unsigned SubReg = 0) const {
108 SubReg,
117 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags | RegState::Define, SubReg);
124 unsigned SubReg = 0) const {
127 return addReg(RegNo, Flags, SubReg);
H A DTargetRegisterInfo.h1074 unsigned SubReg, in shouldCoalesce() argument
1179 unsigned SubReg = 0; variable
1199 unsigned getSubReg() const { return SubReg; } in getSubReg()
1210 SubReg = *Idx++;
1211 if (!SubReg)
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp545 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
546 Reserved.set(SubReg); in getReservedRegs()
552 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
553 Reserved.set(SubReg); in getReservedRegs()
557 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
558 Reserved.set(SubReg); in getReservedRegs()
571 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
572 Reserved.set(SubReg); in getReservedRegs()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp87 unsigned SubReg; member
89 explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {} in RegisterSubReg()
91 : Reg(MO.getReg()), SubReg(MO.getSubReg()) {} in RegisterSubReg()
94 dbgs() << printReg(Reg, TRI, SubReg); in print()
98 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
640 if (DefR.SubReg) { in visitPHI()
673 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC in visitPHI()
1085 if (!R.SubReg) { in getCell()
1937 assert(!DefR.SubReg); in evaluate()
2205 if (!R.SubReg) { in evaluate()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h55 unsigned SubReg, const TargetRegisterClass *DstRC,
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td38 class GP8<GPR SubReg, string n> : PPCReg<n> {
39 let HWEncoding = SubReg.HWEncoding;
40 let SubRegs = [SubReg];
45 class SPE<GPR SubReg, string n> : PPCReg<n> {
46 let HWEncoding = SubReg.HWEncoding;
47 let SubRegs = [SubReg];
69 class VR<VF SubReg, string n> : PPCReg<n> {
70 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
72 let SubRegs = [SubReg];
78 class VSRL<FPR SubReg, string n> : PPCReg<n> {
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