Searched refs:ShiftRHS (Results 1 – 4 of 4) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 5915 const SDValue ShiftRHS = RHS.getOperand(1); in SelectSVERegRegAddrMode() local
5916 if (auto *C = dyn_cast<ConstantSDNode>(ShiftRHS)) in SelectSVERegRegAddrMode()
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| H A D | AArch64ISelLowering.cpp | 15994 uint32_t ShiftRHS = 0; in tryCombineToEXTR() local
15996 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) in tryCombineToEXTR()
16004 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
16009 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
16013 DAG.getConstant(ShiftRHS, DL, MVT::i64)); in tryCombineToEXTR()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6601 MachineOperand &ShiftRHS = ShiftInst->getOperand(2); in selectShiftedRegister() local
6602 auto Immed = getImmedFromMO(ShiftRHS); in selectShiftedRegister()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31339 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL; in LowerRotate() local
31353 DAG.getNode(ShiftRHS, DL, VT, R, DAG.getConstant(4, DL, VT))); in LowerRotate()
31363 DAG.getNode(ShiftRHS, DL, VT, R, DAG.getConstant(6, DL, VT))); in LowerRotate()
31373 DAG.getNode(ShiftRHS, DL, VT, R, DAG.getConstant(7, DL, VT))); in LowerRotate()
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