Searched refs:ShiftLHS (Results 1 – 4 of 4) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 823 MachineInstr *ShiftLHS = in getCmpOperandFoldingProfit() local
829 if (IsSupportedExtend(*ShiftLHS)) in getCmpOperandFoldingProfit()
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| H A D | AArch64InstructionSelector.cpp | 6608 MachineOperand &ShiftLHS = ShiftInst->getOperand(1); in selectShiftedRegister() local
6609 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14936 SDValue ShiftLHS = N->getOperand(0); in isDesirableToCommuteWithShift() local
14942 if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && in isDesirableToCommuteWithShift()
14943 isa<ConstantSDNode>(ShiftLHS.getOperand(1))) { in isDesirableToCommuteWithShift()
14944 uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1); in isDesirableToCommuteWithShift()
14946 SDValue AndLHS = ShiftLHS.getOperand(0); in isDesirableToCommuteWithShift()
15988 uint32_t ShiftLHS = 0; in tryCombineToEXTR() local
15990 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi)) in tryCombineToEXTR()
16004 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
16009 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31338 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate() local
31352 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(4, DL, VT)), in LowerRotate()
31362 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(2, DL, VT)), in LowerRotate()
31372 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(1, DL, VT)), in LowerRotate()
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