| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 109 int ShiftAmount = 0; in generateInstSeqImpl() local
114 ShiftAmount = llvm::countr_zero((uint64_t)Val); in generateInstSeqImpl()
115 Val >>= ShiftAmount; in generateInstSeqImpl()
119 if (ShiftAmount > 12 && !isInt<12>(Val)) { in generateInstSeqImpl()
122 ShiftAmount -= 12; in generateInstSeqImpl()
128 ShiftAmount -= 12; in generateInstSeqImpl()
147 if (ShiftAmount) { in generateInstSeqImpl()
149 Res.emplace_back(Opc, ShiftAmount); in generateInstSeqImpl()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVBaseInfo.h | 253 for (unsigned ShiftAmount = 0; ShiftAmount < 32; ShiftAmount += 8) { in getSPIRVStringOperand() local
254 char c = (Imm >> ShiftAmount) & 0xff; in getSPIRVStringOperand()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 92 Value *ShiftAmount = Builder.CreateTrunc(BI->getOperand(1), Int8Ty); in expand() local
96 Value *Cmp1 = Builder.CreateICmpEQ(ShiftAmount, Int8Zero); in expand()
103 ShiftAmountPHI->addIncoming(ShiftAmount, BB); in expand()
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| H A D | AVRISelLowering.cpp | 301 uint64_t ShiftAmount = in LowerShifts() local
303 if (ShiftAmount == 16) { in LowerShifts()
319 SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8); in LowerShifts()
370 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
379 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
383 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
397 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
402 ShiftAmount -= 4; in LowerShifts()
403 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
404 ShiftAmount < 7) { in LowerShifts()
[all …]
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| /openbsd-src/gnu/llvm/llvm/include/llvm/Support/ |
| H A D | DivisionByConstantInfo.h | 24 unsigned ShiftAmount; ///< shift amount member
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| /openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 177 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
184 .addImm(ShiftAmount); in emitPrologue()
187 .addImm(ShiftAmount); in emitPrologue()
194 .addImm(ShiftAmount); in emitPrologue()
197 .addImm(ShiftAmount); in emitPrologue()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 290 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVSPILL() local
291 if (ShiftAmount != 0) in lowerVSPILL()
294 .addImm(ShiftAmount); in lowerVSPILL()
359 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVRELOAD() local
360 if (ShiftAmount != 0) in lowerVRELOAD()
363 .addImm(ShiftAmount); in lowerVRELOAD()
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| H A D | RISCVInstrInfo.cpp | 2465 uint32_t ShiftAmount = Log2_32(NumOfVReg); in getVLENFactoredAmount() local
2466 if (ShiftAmount == 0) in getVLENFactoredAmount()
2470 .addImm(ShiftAmount) in getVLENFactoredAmount()
2478 uint32_t ShiftAmount; in getVLENFactoredAmount() local
2481 ShiftAmount = Log2_64(NumOfVReg / 9); in getVLENFactoredAmount()
2484 ShiftAmount = Log2_64(NumOfVReg / 5); in getVLENFactoredAmount()
2487 ShiftAmount = Log2_64(NumOfVReg / 3); in getVLENFactoredAmount()
2491 if (ShiftAmount) in getVLENFactoredAmount()
2494 .addImm(ShiftAmount) in getVLENFactoredAmount()
2502 uint32_t ShiftAmount = Log2_32(NumOfVReg - 1); in getVLENFactoredAmount() local
[all …]
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| H A D | RISCVFrameLowering.cpp | 583 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
588 .addImm(ShiftAmount) in emitPrologue()
592 .addImm(ShiftAmount) in emitPrologue()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFrameLowering.cpp | 294 unsigned ShiftAmount = Log2(MFI.getMaxAlign()); in emitPrologue() local
300 .addImm(ShiftAmount) in emitPrologue()
305 .addImm(ShiftAmount) in emitPrologue()
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| /openbsd-src/gnu/llvm/llvm/lib/Support/ |
| H A D | DivisionByConstantInfo.cpp | 63 Retval.ShiftAmount = P - D.getBitWidth(); // resulting shift in get()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.h | 48 unsigned ShiftAmount) const;
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| H A D | MipsTargetStreamer.h | 144 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| H A D | MipsSEISelDAGToDAG.cpp | 283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 274 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
276 if (ShiftAmount >= 32) { in emitDSLL()
277 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
281 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| H A D | MipsMCCodeEmitter.h | 188 template <unsigned ShiftAmount = 0>
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| H A D | MipsMCCodeEmitter.cpp | 751 template <unsigned ShiftAmount>
762 OffBits >>= ShiftAmount; in getMemEncoding()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 968 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
973 if (ShiftAmount >= 8) { in LowerShifts()
993 ShiftAmount -= 8; in LowerShifts()
996 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1000 ShiftAmount -= 1; in LowerShifts()
1003 while (ShiftAmount--) in LowerShifts()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 431 unsigned ShiftAmount; member
612 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
970 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
2172 unsigned ShiftAmount = 0, in CreateReg() argument
2180 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
2191 unsigned ShiftAmount = 0, in CreateVectorReg() argument
2197 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
2277 unsigned ShiftAmount, in CreateShiftedImm() argument
2282 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
3366 int64_t ShiftAmount = getTok().getIntVal(); in tryParseImmWithOptionalShift() local
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 5208 static bool shiftAmountKnownInRange(const Value *ShiftAmount) { in shiftAmountKnownInRange() argument
5209 auto *C = dyn_cast<Constant>(ShiftAmount); in shiftAmountKnownInRange()
7120 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
7122 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
7126 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
7129 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
7141 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
7143 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
7144 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
7158 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1091 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1093 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1094 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| H A D | TargetLowering.cpp | 2135 unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ; in SimplifyDemandedBits() local
2136 SDValue ShAmt = TLO.DAG.getConstant(ShiftAmount, dl, ShiftAmtTy); in SimplifyDemandedBits()
5904 magics.ShiftAmount = 0; in BuildSDIV()
5916 Shifts.push_back(DAG.getConstant(magics.ShiftAmount, dl, ShSVT)); in BuildSDIV()
7155 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
7156 SDValue Shift = DAG.getShiftAmountConstant(ShiftAmount, VT, dl); in expandMUL_LOHI()
8913 SDValue ShiftAmount = in scalarizeVectorLoad() local
8916 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
8998 SDValue ShiftAmount = in scalarizeVectorStore() local
9001 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 918 SDValue ShiftAmount = in PromoteIntRes_ADDSUBSHLSAT() local
921 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
924 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
928 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
3903 SDValue ShiftAmount = DAG.getShiftAmountConstant(Scale % NVTSize, NVT, dl); in ExpandIntRes_MULFIX() local
3905 ShiftAmount); in ExpandIntRes_MULFIX()
3907 ShiftAmount); in ExpandIntRes_MULFIX()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1915 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
1916 if (ShiftAmount == Power) in factorOutPowerOf2()
1918 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCasts.cpp | 547 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
549 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
560 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
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