| /openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
|
| H A D | X86ISelLowering.cpp | 25456 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG); in LowerXALUO() local
25458 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); in LowerXALUO()
27388 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
27391 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
27393 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
27397 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
27399 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
27404 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
27409 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
27414 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrP10.td | 1889 multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
1892 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1894 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1896 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1898 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1900 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1903 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
1905 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
1907 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
1909 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
[all …]
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| H A D | PPCInstrInfo.td | 3761 multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {
3762 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3764 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3766 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
3768 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
3770 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
3772 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
3774 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
3777 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
3779 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 662 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
664 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
665 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
689 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
692 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
693 SetCC.getOperand(1), in performSELECTCombine()
694 ISD::getSetCCInverse(CC, SetCC.getValueType())); in performSELECTCombine()
696 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
719 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
726 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
[all …]
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| H A D | MipsSEISelLowering.cpp | 978 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
980 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
984 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
985 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
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| H A D | MipsInstrInfo.td | 1519 // SetCC
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| /openbsd-src/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VVPInstrInfo.td | 104 // SetCC (lhs, rhs, cc, mask, vl)
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1442 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO() local
1446 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC); in LowerXALUO()
1977 SDValue SetCC = in LowerSETCC() local
1981 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
1982 return SetCC; in LowerSETCC()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 756 SDValue SetCC = in Expand() local
759 Results.push_back(DAG.getSelect(SDLoc(Node), Node->getValueType(0), SetCC, in Expand()
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| H A D | DAGCombiner.cpp | 2353 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
2354 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in foldAddSubBoolOfMaskedVal()
2355 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) || in foldAddSubBoolOfMaskedVal()
2356 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2357 !isOneConstant(SetCC.getOperand(0).getOperand(1))) in foldAddSubBoolOfMaskedVal()
2366 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT); in foldAddSubBoolOfMaskedVal()
8752 SDValue SetCC = in visitXOR() local
8755 CombineTo(N, SetCC); in visitXOR()
8756 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); in visitXOR()
11930 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1178 SDValue SetCC; in PromoteIntRes_SETCC() local
1183 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers); in PromoteIntRes_SETCC()
1186 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1188 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1192 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
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| H A D | TargetLowering.cpp | 9909 SDValue SetCC; in expandUADDSUBO() local
9916 SetCC = in expandUADDSUBO()
9921 SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO()
9923 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
9944 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
9945 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
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| H A D | SelectionDAGBuilder.cpp | 7283 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, in visitIntrinsicCall() local
7285 setValue(&I, SetCC); in visitIntrinsicCall()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18365 const SDValue SetCC = N->getOperand(0); in performSignExtendSetCCCombine() local
18367 const SDValue CCOp0 = SetCC.getOperand(0); in performSignExtendSetCCCombine()
18368 const SDValue CCOp1 = SetCC.getOperand(1); in performSignExtendSetCCCombine()
18374 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get(); in performSignExtendSetCCCombine()
18379 if (isCheapToExtend(SetCC.getOperand(0)) && in performSignExtendSetCCCombine()
18380 isCheapToExtend(SetCC.getOperand(1))) { in performSignExtendSetCCCombine()
18387 SDLoc(SetCC), N->getValueType(0), Ext1, Ext2, in performSignExtendSetCCCombine()
18388 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get()); in performSignExtendSetCCCombine()
20525 SDValue SetCC = N->getOperand(0); in trySwapVSelectOperands() local
20526 if (SetCC.getOpcode() != ISD::SETCC || !SetCC.hasOneUse()) in trySwapVSelectOperands()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4950 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
4953 return SetCC; in lowerICMPIntrinsic()
4954 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
4980 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic() local
4983 return SetCC; in lowerFCMPIntrinsic()
4984 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
5223 SDNode *SetCC = nullptr; in LowerBRCOND() local
5227 SetCC = Intr; in LowerBRCOND()
5228 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
5246 assert(!SetCC || in LowerBRCOND()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3986 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
3988 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
3990 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4052 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerADDSUBCARRY() local
4054 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerADDSUBCARRY()
4056 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerADDSUBCARRY()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3128 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
3133 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4141 SDValue SetCC = DAG.getSetCC( in LowerOperation() local
4143 return DAG.getLogicalNOT(DL, SetCC, VT); in LowerOperation()
5960 SDValue SetCC = DAG.getSetCC(DL, XLenVT, Vec, Zero, CC); in lowerVectorMaskVecReduction() local
5963 return SetCC; in lowerVectorMaskVecReduction()
5971 return DAG.getNode(BaseOpc, DL, XLenVT, SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13049 SDValue SetCC; in PerformSELECTCombine() local
13058 SetCC = N->getOperand(0); in PerformSELECTCombine()
13059 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
13060 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
13061 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()
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