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Searched refs:SchedWrite (Results 1 – 25 of 38) sorted by relevance

12

/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
17 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
18 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
19 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
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H A DRISCVScheduleZb.td12 def WriteSHXADD : SchedWrite; // sh1add/sh2add/sh3add
13 def WriteSHXADD32 : SchedWrite; // sh1add.uw/sh2add.uw/sh3add.uw
16 def WriteRotateImm : SchedWrite;
17 def WriteRotateImm32 : SchedWrite;
18 def WriteRotateReg : SchedWrite;
19 def WriteRotateReg32 : SchedWrite;
20 def WriteCLZ : SchedWrite;
21 def WriteCLZ32 : SchedWrite;
22 def WriteCTZ : SchedWrite;
23 def WriteCTZ32 : SchedWrite;
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H A DRISCVScheduleV.td18 // Creates SchedWrite for each (name, LMUL) pair for LMUL in SchedMxList
21 def name # "_" # mx : SchedWrite;
25 // Creates SchedWrite for each (name, LMUL) pair for LMUL in SchedMxListW
28 def name # "_" # mx : SchedWrite;
32 // Creates SchedWrite for each (name, LMUL) pair for LMUL in SchedMxListFW
35 def name # "_" # mx : SchedWrite;
64 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
72 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
80 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
86 multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []> {
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H A DRISCVInstrInfoVPseudos.td1672 defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
1751 defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
1807 defvar WriteVMPopV_MX = !cast<SchedWrite>("WriteVMPopV_" # mx);
1822 defvar WriteVMFFSV_MX = !cast<SchedWrite>("WriteVMFFSV_" # mx);
1838 defvar WriteVMSFSV_MX = !cast<SchedWrite>("WriteVMSFSV_" # mx);
1852 defvar WriteVMIdxV_MX = !cast<SchedWrite>("WriteVMIdxV_" # mx);
1870 defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
1884 defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx);
1901 defvar WriteVCompressV_MX = !cast<SchedWrite>("WriteVCompressV_" # mx);
1982 defvar WriteVGatherV_MX = !cast<SchedWrite>("WriteVGatherV_" # mx);
[all …]
H A DRISCVInstrInfoF.td158 SchedWrite sw>
166 SchedWrite sw>
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td14 def NormalGr : SchedWrite;
15 def Cracked : SchedWrite;
16 def GroupAlone : SchedWrite;
17 def GroupAlone2 : SchedWrite;
18 def GroupAlone3 : SchedWrite;
19 def BeginGroup : SchedWrite;
20 def EndGroup : SchedWrite;
22 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
23 def LSULatency : SchedWrite;
26 foreach L = 1 - 30 in def "WLat"#L : SchedWrite;
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H A DSystemZScheduleZ13.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
H A DSystemZScheduleZ15.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z15_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z15_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z15_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z15_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z15_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
H A DSystemZScheduleZ14.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
H A DSystemZScheduleZ16.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z16_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z16_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z16_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z16_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z16_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z16_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z16_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z16_VecUnit]>;
H A DSystemZScheduleZEC12.td68 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
87 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
90 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
H A DSystemZScheduleZ196.td68 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
86 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
87 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td20 def WriteImm : SchedWrite; // MOVN, MOVZ
24 def WriteI : SchedWrite; // ALU
25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
30 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
32 def WriteIS : SchedWrite; // Shift/Scale
33 def WriteID32 : SchedWrite; // 32-bit Divide
34 def WriteID64 : SchedWrite; // 64-bit Divide
36 def WriteIM32 : SchedWrite; // 32-bit Multiply
37 def WriteIM64 : SchedWrite; // 64-bit Multiply
[all …]
H A DAArch64SchedThunderX.td46 // Subtarget-specific SchedWrite types mapping the ProcResources and
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86Schedule.td28 def WriteRMW : SchedWrite;
30 // Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
31 multiclass X86WriteRes<SchedWrite SchedRW,
41 // Most instructions can fold loads, so almost every SchedWrite comes in two
43 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
45 class X86FoldableSchedWrite : SchedWrite {
46 // The SchedWrite to use when a load is folded into the instruction.
47 SchedWrite Folded;
56 def Ld : SchedWrite;
59 let Folded = !cast<SchedWrite>(NAME#"Ld");
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H A DX86ScheduleZnver4.td400 multiclass __Zn4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
428 multiclass Zn4WriteResInt<SchedWrite SchedRW,
434 multiclass Zn4WriteResXMM<SchedWrite SchedRW,
440 multiclass Zn4WriteResYMM<SchedWrite SchedRW,
446 multiclass Zn4WriteResZMM<SchedWrite SchedRW,
H A DX86ScheduleZnver3.td401 multiclass __zn3WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
429 multiclass Zn3WriteResInt<SchedWrite SchedRW,
435 multiclass Zn3WriteResXMM<SchedWrite SchedRW,
441 multiclass Zn3WriteResYMM<SchedWrite SchedRW,
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMSchedule.td31 // def WriteALUsr : SchedWrite;
60 def WriteALU : SchedWrite;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
66 def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
70 def WriteCMP : SchedWrite;
71 def WriteCMPsi : SchedWrite;
72 def WriteCMPsr : SchedWrite;
75 def WriteMUL16 : SchedWrite; // 16-bit multiply.
76 def WriteMUL32 : SchedWrite; // 32-bit multiply.
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H A DARMScheduleM4.td37 class M4UnitL1<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 1; }
38 class M4UnitL2<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 2; }
39 class M4UnitL3<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 3; }
40 class M4UnitL14<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 14; }
H A DARMScheduleA9.td2086 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2088 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2151 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2156 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2186 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2191 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSISchedule.td19 def WriteBranch : SchedWrite;
20 def WriteExport : SchedWrite;
21 def WriteLDS : SchedWrite;
22 def WriteSALU : SchedWrite;
23 def WriteSMEM : SchedWrite;
24 def WriteVMEM : SchedWrite;
25 def WriteBarrier : SchedWrite;
31 def Write32Bit : SchedWrite;
33 def WriteFloatCvt : SchedWrite;
35 def WriteTrans32 : SchedWrite;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td57 def WriteLD : SchedWrite;
58 def WriteST : SchedWrite;
59 def WriteLDSW : SchedWrite;
60 def WriteSTSW : SchedWrite;
61 def WriteALU : SchedWrite;
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSchedule.td211 // instruction. One SchedWrite type must be listed for each explicit
212 // def operand in order. Additional SchedWrite types may optionally be
219 // single SchedWrite and single SchedRead in any order.
225 class SchedWrite : SchedReadWrite;
226 def NoWrite : SchedWrite;
231 // Define a SchedWrite that is modeled as a sequence of other
241 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
242 list<SchedWrite> Writes = writes;
270 // Define the resources and latency of a SchedWrite. This will be used
272 // SchedWrite is defined by the target, while WriteResources is
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/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp108 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
864 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
868 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
869 return SchedWrite.TheDef; in FindWriteResources()
872 for (Record *A : SchedWrite.Aliases) { in FindWriteResources()
895 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
909 SchedWrite.TheDef->getName()); in FindWriteResources()
H A DCodeGenSchedule.cpp802 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); in expandRWSeqForProc() local
804 for (const Record *Rec : SchedWrite.Aliases) { in expandRWSeqForProc()
822 if (!SchedWrite.IsSequence) { in expandRWSeqForProc()
827 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc()
829 for (unsigned Idx : SchedWrite.Sequence) { in expandRWSeqForProc()

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