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Searched refs:SWR (Results 1 – 10 of 10) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp241 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td164 def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>;
/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp1912 for (Record *SWR : SWRDefs) { in collectProcResources()
1913 Record *ModelDef = SWR->getValueAsDef("SchedModel"); in collectProcResources()
1914 addWriteRes(SWR, getProcModel(ModelDef).Index); in collectProcResources()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsISelLowering.h251 SWR, enumerator
H A DMipsInstructionSelector.cpp473 if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) in select()
H A DMipsISelLowering.cpp216 case MipsISD::SWR: return "MipsISD::SWR"; in getTargetNodeName()
2774 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
4936 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_W()
5020 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_D()
5028 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_D()
H A DMipsScheduleP5600.td144 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>;
H A DMipsScheduleGeneric.td576 def : InstRW<[GenericWriteStore], (instrs SWL, SWR)>;
H A DMipsInstrInfo.td144 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
2157 def SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4562 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()