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Searched refs:SOffset (Results 1 – 17 of 17) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h168 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
171 SDValue &SOffset, SDValue &Offset) const;
173 SDValue &VAddr, SDValue &SOffset,
198 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue *SOffset,
202 bool SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase, SDValue *SOffset,
205 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue *SOffset,
209 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &SOffset) const;
210 bool SelectSMRDSgprImm(SDValue Addr, SDValue &SBase, SDValue &SOffset,
214 bool SelectSMRDBufferSgprImm(SDValue N, SDValue &SOffset,
H A DAMDGPUISelDAGToDAG.cpp1238 SDValue &SOffset, SDValue &Offset, in SelectMUBUF() argument
1251 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUF()
1314 SOffset = in SelectMUBUF()
1323 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64() argument
1332 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64)) in SelectMUBUFAddr64()
1365 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen() argument
1385 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUFScratchOffen()
1416 std::tie(VAddr, SOffset) = foldFrameIndex(N0); in SelectMUBUFScratchOffen()
1423 std::tie(VAddr, SOffset) = foldFrameIndex(Addr); in SelectMUBUFScratchOffen()
1441 SDValue &SOffset, in SelectMUBUFScratchOffset() argument
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H A DAMDGPUInstructionSelector.h200 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
271 Register &SOffset, int64_t &ImmOffset) const;
276 Register &RSrcReg, Register &SOffset,
280 Register &SOffset, int64_t &Offset) const;
H A DSIRegisterInfo.cpp895 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex() local
896 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1324 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1395 if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) { in buildSpillLoadStore()
1396 SOffset = MCRegister(); in buildSpillLoadStore()
1403 SOffset = RS->scavengeRegisterBackwards(AMDGPU::SGPR_32RegClass, MI, false, 0, false); in buildSpillLoadStore()
1411 SOffset = Reg; in buildSpillLoadStore()
1418 SOffset = Register(); in buildSpillLoadStore()
1420 if (!SOffset) { in buildSpillLoadStore()
1436 } else if (!SOffset && CanClobberSCC) { in buildSpillLoadStore()
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H A DAMDGPUInstructionSelector.cpp3773 Register *SOffset, in selectSmrdOffset() argument
3790 if (SOffset && Offset) { in selectSmrdOffset()
3798 *SOffset = OffsetReg; in selectSmrdOffset()
3814 if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) && in selectSmrdOffset()
3821 *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdOffset()
3822 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset) in selectSmrdOffset()
3827 if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) { in selectSmrdOffset()
3830 *SOffset = OffsetReg; in selectSmrdOffset()
3872 Register Base, SOffset; in selectSmrdSgpr() local
3873 if (!selectSmrdOffset(Root, Base, &SOffset, /* Offset= */ nullptr)) in selectSmrdSgpr()
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H A DAMDGPULegalizerInfo.h169 Register SOffset, unsigned ImmOffset, Register VIndex,
H A DAMDGPULegalizerInfo.cpp4274 Register VOffset, Register SOffset, in updateBufferMMO() argument
4280 getIConstantVRegValWithLookThrough(SOffset, MRI); in updateBufferMMO()
4418 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
4429 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferStore()
4457 .addUse(SOffset) // soffset in legalizeBufferStore()
4472 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad() argument
4481 .addUse(SOffset) // soffset in buildBufferLoad()
4529 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
4546 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferLoad()
4586 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
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H A DAMDGPURegisterBankInfo.cpp1258 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1259 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1262 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1267 return SOffset + ImmOffset; in setBufferOffsets()
1277 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1278 if ((int)Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
1282 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1289 if (SOffset == 0) { in setBufferOffsets()
1368 Register SOffset; in applyMappingSBufferLoad() local
1373 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
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H A DSILoadStoreOptimizer.cpp97 bool SOffset = false; member
610 Result.SOffset = true; in getRegs()
636 Result.SOffset = true; in getRegs()
652 Result.SOffset = true; in getRegs()
772 if (Regs.SOffset) in setMI()
H A DGCNHazardRecognizer.cpp829 const MachineOperand *SOffset = in createsVALUHazard() local
834 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DSIInstrInfo.cpp379 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
381 if (SOffset) { in getMemOperandsWithOffsetWidth()
382 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
383 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
385 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
6091 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
6106 .add(*SOffset) in legalizeOperands()
6130 .add(*SOffset) in legalizeOperands()
H A DSIISelLowering.cpp7175 SDValue SOffset, SDValue Offset, in updateBufferMMO() argument
7177 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in updateBufferMMO()
7194 cast<ConstantSDNode>(SOffset)->getSExtValue() + in updateBufferMMO()
8536 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
8537 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, in setBufferOffsets()
8540 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
8548 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
8550 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
8553 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp721 unsigned SOffset = 0; in getMachineOpValue() local
738 ++SOffset; in getMachineOpValue()
764 : SOffset; in getMachineOpValue()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp330 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
332 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h1285 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPUBaseInfo.cpp2566 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
2601 SOffset = Overflow; in splitMUBUFOffset()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4650 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
4701 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
4743 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
4745 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
4747 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()