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Searched refs:SF (Results 1 – 25 of 236) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.h32 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
33 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
34 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
35 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
36 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
37 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
38 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
39 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
40 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
41 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
H A Ddcn32_mmhubbub.h86 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
87 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
88 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
89 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
90 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
91 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
92 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
93 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
94 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
95 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
[all …]
H A Ddcn32_mpc.h180 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
181 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
182 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
183 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
184 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
185 SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL, mask_sh),\
186 SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, mask_sh),\
187 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
188 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
189 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h136 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
137 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
138 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
139 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
140 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
142 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
143 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
144 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
145 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
[all …]
H A Ddcn30_optc.h117 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
118 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
119 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
120 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
121 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
122 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
123 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
124 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
125 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
126 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
H A Ddcn30_mpc.h429 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
430 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
431 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
432 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
433 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
434 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
435 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
436 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
437 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
438 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.h105 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
107 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
108 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
110 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
113 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
114 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.h104 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
105 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
107 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
108 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
110 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
113 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.h91 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
92 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
93 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
94 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
95 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
96 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
97 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
98 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
99 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
100 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
[all …]
H A Ddcn20_optc.h50 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
51 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
52 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
53 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
55 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
56 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
58 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
59 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
[all …]
H A Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
141 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
142 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
143 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
[all …]
H A Ddcn20_vmid.h41 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
42 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
43 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
44 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
45 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh)…
46 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh…
47 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
48 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h47 #define SF(reg_name, field_name, post_fix)\ macro
85 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
86 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
87 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
88 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
89 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
91 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
92 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
93 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
[all …]
H A Ddcn10_optc.h195 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
196 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
197 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
198 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
199 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
200 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
201 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
202 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
203 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
204 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
[all …]
H A Ddcn10_mpc.h64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
71 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.h46 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
47 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
48 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
49 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
50 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
51 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
52 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
53 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
54 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
55 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
49 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
[all …]
/openbsd-src/gnu/llvm/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp41 static void SetValue(Value *V, GenericValue Val, ExecutionContext &SF) { in SetValue() argument
42 SF.Values[V] = Val; in SetValue()
63 ExecutionContext &SF = ECStack.back(); in visitUnaryOperator() local
65 GenericValue Src = getOperandValue(I.getOperand(0), SF); in visitUnaryOperator()
96 SetValue(&I, R, SF); in visitUnaryOperator()
333 ExecutionContext &SF = ECStack.back(); in visitICmpInst() local
335 GenericValue Src1 = getOperandValue(I.getOperand(0), SF); in visitICmpInst()
336 GenericValue Src2 = getOperandValue(I.getOperand(1), SF); in visitICmpInst()
355 SetValue(&I, R, SF); in visitICmpInst()
666 ExecutionContext &SF = ECStack.back(); in visitFCmpInst() local
[all …]
H A DInterpreter.h189 gep_type_iterator E, ExecutionContext &SF);
195 void SwitchToNewBasicBlock(BasicBlock *Dest, ExecutionContext &SF);
201 GenericValue getConstantExprValue(ConstantExpr *CE, ExecutionContext &SF);
202 GenericValue getOperandValue(Value *V, ExecutionContext &SF);
204 ExecutionContext &SF);
206 ExecutionContext &SF);
208 ExecutionContext &SF);
210 ExecutionContext &SF);
212 ExecutionContext &SF);
214 ExecutionContext &SF);
[all …]
/openbsd-src/gnu/gcc/gcc/config/arm/
H A Dfpa.md101 [(set (match_operand:SF 0 "s_register_operand" "=f,f")
102 (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
103 (match_operand:SF 2 "arm_float_add_operand" "fG,H")))]
127 (match_operand:SF 1 "s_register_operand" "f,f"))
141 (match_operand:SF 2 "s_register_operand" "f"))))]
151 (match_operand:SF 1 "s_register_operand" "f"))
153 (match_operand:SF 2 "s_register_operand" "f"))))]
161 [(set (match_operand:SF 0 "s_register_operand" "=f,f")
162 (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
163 (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
[all …]
H A Dvfp.md188 [(set (match_operand:SF 0 "nonimmediate_operand" "=w,?r,w ,Uv,r ,m,w,r")
189 (match_operand:SF 1 "general_operand" " ?r,w,UvE,w, mE,r,w,r"))]
250 [(set (match_operand:SF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
251 (if_then_else:SF
254 (match_operand:SF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
255 (match_operand:SF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
299 [(set (match_operand:SF 0 "s_register_operand" "=w")
300 (abs:SF (match_operand:SF 1 "s_register_operand" "w")))]
317 [(set (match_operand:SF 0 "s_register_operand" "=w,?r")
318 (neg:SF (match_operand:SF 1 "s_register_operand" "w,r")))]
[all …]
H A Dcirrus.md54 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
55 (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
56 (match_operand:SF 2 "cirrus_fp_register" "v")))]
94 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
95 (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
96 (match_operand:SF 2 "cirrus_fp_register" "v")))]
159 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
160 (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
161 (match_operand:SF 2 "cirrus_fp_register" "v")))]
259 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
[all …]
/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DSubtargetFeatureInfo.cpp56 for (const auto &SF : SubtargetFeatures) { in emitSubtargetFeatureBitEnumeration() local
57 const SubtargetFeatureInfo &SFI = SF.second; in emitSubtargetFeatureBitEnumeration()
69 for (const auto &SF : SubtargetFeatures) in emitNameTable() local
70 if (IndexUB <= SF.second.Index) in emitNameTable()
71 IndexUB = SF.second.Index+1; in emitNameTable()
76 for (const auto &SF : SubtargetFeatures) in emitNameTable() local
77 Names[SF.second.Index] = SF.second.getEnumName(); in emitNameTable()
99 for (const auto &SF : SubtargetFeatures) { in emitComputeAvailableFeatures() local
100 const SubtargetFeatureInfo &SFI = SF.second; in emitComputeAvailableFeatures()
155 for (const auto &SF : SubtargetFeatures) { in emitComputeAssemblerAvailableFeatures() local
[all …]
/openbsd-src/gnu/gcc/gcc/config/xtensa/
H A Dxtensa.md45 "unknown,none,QI,HI,SI,DI,SF,DF,BL"
196 [(set (match_operand:SF 0 "register_operand" "=f")
197 (plus:SF (match_operand:SF 1 "register_operand" "%f")
198 (match_operand:SF 2 "register_operand" "f")))]
202 (set_attr "mode" "SF")
283 [(set (match_operand:SF 0 "register_operand" "=f")
284 (minus:SF (match_operand:SF 1 "register_operand" "f")
285 (match_operand:SF 2 "register_operand" "f")))]
289 (set_attr "mode" "SF")
360 [(set (match_operand:SF 0 "register_operand" "=f")
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/config/xtensa/
H A Dxtensa.md54 "unknown,none,QI,HI,SI,DI,SF,DF,BL"
192 [(set (match_operand:SF 0 "register_operand" "=f")
193 (plus:SF (match_operand:SF 1 "register_operand" "%f")
194 (match_operand:SF 2 "register_operand" "f")))]
198 (set_attr "mode" "SF")
286 [(set (match_operand:SF 0 "register_operand" "=f")
287 (minus:SF (match_operand:SF 1 "register_operand" "f")
288 (match_operand:SF 2 "register_operand" "f")))]
292 (set_attr "mode" "SF")
369 [(set (match_operand:SF 0 "register_operand" "=f")
[all …]

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