Searched refs:SCR1 (Results 1 – 3 of 3) sorted by relevance
1 //==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//11 // SCR1: https://github.com/syntacore/scr117 // SCR1 is single-issue in-order processor64 // Load/store instructions on SCR1 have latency 2 and inverse throughput 2
1355 #define SCR1 (*(volatile char *)(0x05FFFECA)) /* Channel 1 serial control register */ macro1505 SCR1 &= ~(SCI_TE | SCI_RE); in init_serial()1512 SCR1 &= ~(SCI_CKE1 | SCI_CKE0); in init_serial()1520 SCR1 |= SCI_RE | SCI_TE; in init_serial()
255 * A Syntacore SCR1 CPU model was added.