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Searched refs:RegType (Results 1 – 6 of 6) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td5899 string kind2, RegisterOperand RegType,
5902 BaseSIMDThreeSameVectorTied<Q, U, 0b100, {0b1001, Mixed}, RegType, asm, kind1,
5903 [(set (AccumType RegType:$dst),
5904 (OpNode (AccumType RegType:$Rd),
5905 (InputType RegType:$Rn),
5906 (InputType RegType:$Rm)))]> {
5922 string kind2, RegisterOperand RegType,
5925 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
5926 [(set (AccumType RegType:$dst),
5927 (OpNode (AccumType RegType:$Rd),
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H A DAArch64FrameLowering.cpp2502 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
H A DAArch64InstrInfo.td1113 string rhs_kind, RegisterOperand RegType,
1116 lhs_kind, rhs_kind, RegType, AccumType,
1118 let Pattern = [(set (AccumType RegType:$dst),
1119 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd),
1123 (InputType RegType:$Rn))))];
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7151 MVT RegType = TLI->getPreferredSwitchConditionType(Context, OldVT); in optimizeSwitchType() local
7152 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType()
7171 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchType()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3509 char RegType = RegTypes[RegNo / 8]; in getRegForInlineAsmConstraint() local
3511 char Tmp[] = {'{', RegType, RegIndex, '}', 0}; in getRegForInlineAsmConstraint()
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTarget.td227 // RegType - Specify the list ValueType of the registers in this register