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Searched refs:RegClassID (Results 1 – 14 of 14) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp104 unsigned RegClassID; in Select() local
111 RegClassID = R600::R600_Reg64RegClassID; in Select()
115 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
117 RegClassID = R600::R600_Reg128RegClassID; in Select()
122 SelectBuildVector(N, RegClassID); in Select()
H A DAMDGPUISelDAGToDAG.h112 void SelectBuildVector(SDNode *N, unsigned RegClassID);
H A DAMDGPUISelDAGToDAG.cpp441 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
446 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
463 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
568 unsigned RegClassID = in Select() local
570 SelectBuildVector(N, RegClassID); in Select()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h108 const char* getRegClassName(unsigned RegClassID) const;
111 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
H A DAMDGPUDisassembler.cpp1084 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
1086 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1105 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
1107 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
1109 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1100 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1160 bool parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo);
1629 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1631 switch (RegClassID) { in GetSIDIForRegClass()
1665 int RegClassID = -1; in VerifyAndAdjustOperands() local
1686 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1687 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1693 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1695 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1697 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp518 unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass; in scavengeRegister() local
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
H A DAArch64RegisterInfo.td660 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
906 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
934 # RegClass # "RegClassID>";
1068 # RegClassSuffix # "RegClassID>";
1109 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1467 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1608 # EltSize # ", AArch64::" # RC # "RegClassID>";
1635 # EltSize # ", AArch64::" # RC # "RegClassID>";
1670 # EltSize # ", AArch64::" # RC # "RegClassID>";
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1009 unsigned RegClassID; in convertVRToVRMx() local
1011 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1013 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1015 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1019 &RISCVMCRegisterClasses[RegClassID]); in convertVRToVRMx()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp224 unsigned RegClassID; in createTuple() local
236 RegClassID = M1TupleRegClassIDs[NF - 2]; in createTuple()
242 RegClassID = M2TupleRegClassIDs[NF - 2]; in createTuple()
248 RegClassID = RISCV::VRN2M4RegClassID; in createTuple()
255 Ops.push_back(CurDAG.getTargetConstant(RegClassID, DL, MVT::i32)); in createTuple()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp77 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { in isMemOperand() argument
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1895 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1902 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1370 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1372 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1375 template <unsigned RegClassID, int ExtWidth>
1380 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1853 template<unsigned Bits, unsigned RegClassID>
1856 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()