| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVSDPatterns.td | 114 vti.LMul, vti.AVL, vti.RegClass>;
117 vti.LMul, vti.AVL, vti.RegClass,
128 vti.LMul, vti.AVL, vti.RegClass,
155 vti.LMul, vti.AVL, vti.RegClass>;
158 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
166 (fvti.Vector fvti.RegClass:$rs1))),
168 fvti.RegClass:$rs1,
177 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
178 (vti.Vector vti.RegClass:$rs2), cc)),
179 (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
[all …]
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| H A D | RISCVInstrInfoVVLPatterns.td | 506 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
507 vti.RegClass>;
510 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
521 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
533 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
534 vti.RegClass>;
537 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
549 vti.LMul, wti.RegClass, vti.RegClass>;
552 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
553 vti.RegClass>;
[all …]
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| H A D | RISCVInstrInfoVPseudos.td | 190 VReg RegClass = Reg;
930 class VPseudoNullaryNoMask<VReg RegClass>:
931 Pseudo<(outs RegClass:$rd),
942 class VPseudoNullaryNoMaskTU<VReg RegClass>:
943 Pseudo<(outs RegClass:$rd),
944 (ins RegClass:$merge, AVL:$vl, ixlenimm:$sew),
956 class VPseudoNullaryMask<VReg RegClass>:
957 Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
958 (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
4136 vti.Log2SEW, vti.LMul, vti.RegClass,
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| H A D | RISCVInstrInfoXTHead.td | 112 wti.RegClass, vti.RegClass, vti.RegClass>;
125 wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
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| /openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/ |
| H A D | RegisterAliasing.cpp | 33 const MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
78 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass)); in getRegisterClass()
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| H A D | MCInstrDescView.cpp | 119 if (OpInfo.RegClass >= 0) in create()
120 Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass); in create()
272 &RegInfo.getRegClass(Op.Info->RegClass)) in dump()
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| H A D | RegisterAliasing.h | 45 const MCRegisterClass &RegClass);
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRInstPrinter.cpp | 104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVMCCodeEmitter.cpp | 70 return (DefOpInfo.RegClass == SPIRV::IDRegClassID || in hasType()
71 DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) && in hasType()
72 FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID; in hasType()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | RDFRegisters.cpp | 36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
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| H A D | RegisterClassInfo.cpp | 51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
128 RCInfo &RCI = RegClass[RC->getID()]; in compute()
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| H A D | MachineRegisterInfo.cpp | 157 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
159 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
160 assert(RegClass->isAllocatable() && in createVirtualRegister()
165 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
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| H A D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
142 Register NewVReg = MRI->createVirtualRegister(RegClass); in INITIALIZE_PASS_DEPENDENCY()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyPeephole.cpp | 98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
99 CopyLocalOpc = WebAssembly::getCopyOpcodeForRegClass(RegClass); in maybeRewriteToFallthrough()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
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| H A D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
106 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
109 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
117 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
122 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
646 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
647 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
648 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
651 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrArithmetic.td | 552 /// RegClass - This is the register class associated with this type. For
554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
660 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
668 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
[all …]
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
79 const RCInfo &RCI = RegClass[RC->getID()]; in get()
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| H A D | RegisterScavenging.h | 175 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
177 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegisterBanks.td | 10 // as InstructionSelector RegClass checking code relies on them
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | 1885 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1886 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1887 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1952 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
1953 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2012 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2013 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2014 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2126 const TargetRegisterClass *RegClass = in createEntryPHI() local
2128 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass); in createEntryPHI()
[all …]
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| H A D | SIInstrInfo.cpp | 1073 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate() local
1074 if (RegClass == &AMDGPU::SReg_32RegClass || in materializeImmediate()
1075 RegClass == &AMDGPU::SGPR_32RegClass || in materializeImmediate()
1076 RegClass == &AMDGPU::SReg_32_XM0RegClass || in materializeImmediate()
1077 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) { in materializeImmediate()
1083 if (RegClass == &AMDGPU::SReg_64RegClass || in materializeImmediate()
1084 RegClass == &AMDGPU::SGPR_64RegClass || in materializeImmediate()
1085 RegClass == &AMDGPU::SReg_64_XEXECRegClass) { in materializeImmediate()
1091 if (RegClass == &AMDGPU::VGPR_32RegClass) { in materializeImmediate()
1096 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) { in materializeImmediate()
[all …]
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| /openbsd-src/gnu/llvm/llvm/utils/TableGen/ |
| H A D | CompressInstEmitter.cpp | 130 bool validateRegister(Record *Reg, Record *RegClass);
150 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
152 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
154 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); in validateRegister()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmTypeCheck.cpp | 336 auto VT = WebAssembly::regClassToValType(Op.RegClass); in typeCheck()
345 auto VT = WebAssembly::regClassToValType(Op.RegClass); in typeCheck()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 92 const TargetRegisterClass &RegClass);
108 const TargetRegisterClass &RegClass,
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 544 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
725 (FrameReg.isVirtual() || RegClass->contains(FrameReg))) { in rewriteT2FrameIndex()
729 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
765 return Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg)); in rewriteT2FrameIndex()
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