Searched refs:Reg1Op (Results 1 – 1 of 1) sorted by relevance
1626 const MachineOperand &Reg1Op = MI.getOperand(1); in MergeBaseUpdateLSDouble() local1627 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base) in MergeBaseUpdateLSDouble()1654 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble()1657 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); in MergeBaseUpdateLSDouble()