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Searched refs:RW (Results 1 – 25 of 98) sorted by relevance

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/openbsd-src/sys/arch/luna88k/luna88k/
H A Dpmap_table.c38 #define RW (PROT_READ | PROT_WRITE) macro
50 { NVRAM_ADDR, NVRAM_SPACE, RW, CI },
51 { NVRAM_ADDR_88K2, PAGE_SIZE, RW, CI },
52 { OBIO_PIO0_BASE, PAGE_SIZE, RW, CI },
53 { OBIO_PIO1_BASE, PAGE_SIZE, RW, CI },
54 { OBIO_SIO, PAGE_SIZE, RW, CI },
55 { OBIO_TAS, PAGE_SIZE, RW, CI },
56 { OBIO_CLOCK0, PAGE_SIZE, RW, CI },
57 { INT_ST_MASK0, PAGE_SIZE, RW, CI },
58 { SOFT_INT0, PAGE_SIZE, RW, CI },
[all …]
/openbsd-src/sys/dev/ic/
H A Dar9285.c208 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI); in ar9285_init_from_rom()
209 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ); in ar9285_init_from_rom()
214 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9285_init_from_rom()
216 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9285_init_from_rom()
218 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, in ar9285_init_from_rom()
220 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9285_init_from_rom()
226 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9285_init_from_rom()
228 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9285_init_from_rom()
230 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, in ar9285_init_from_rom()
232 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9285_init_from_rom()
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H A Dar9380.c312 reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL, in ar9380_init_from_rom()
317 reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL, in ar9380_init_from_rom()
321 reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB, in ar9380_init_from_rom()
329 reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon); in ar9380_init_from_rom()
332 reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2); in ar9380_init_from_rom()
338 reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]); in ar9380_init_from_rom()
345 reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL, in ar9380_init_from_rom()
363 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5); in ar9380_init_from_rom()
364 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5); in ar9380_init_from_rom()
365 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5); in ar9380_init_from_rom()
[all …]
H A Dar9287.c185 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar9287_init_from_rom()
187 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar9287_init_from_rom()
192 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9287_init_from_rom()
194 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9287_init_from_rom()
199 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, in ar9287_init_from_rom()
201 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, in ar9287_init_from_rom()
208 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); in ar9287_init_from_rom()
210 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); in ar9287_init_from_rom()
214 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); in ar9287_init_from_rom()
224 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); in ar9287_init_from_rom()
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H A Dar9280.c228 reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1); in ar9280_set_synth()
264 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar9280_init_from_rom()
266 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar9280_init_from_rom()
272 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9280_init_from_rom()
274 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9280_init_from_rom()
276 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, in ar9280_init_from_rom()
278 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9280_init_from_rom()
287 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, in ar9280_init_from_rom()
289 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, in ar9280_init_from_rom()
295 reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob); in ar9280_init_from_rom()
[all …]
H A Dar5416.c262 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar5416_init_from_rom()
264 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar5416_init_from_rom()
273 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN, in ar5416_init_from_rom()
275 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN, in ar5416_init_from_rom()
284 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); in ar5416_init_from_rom()
288 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN, in ar5416_init_from_rom()
293 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); in ar5416_init_from_rom()
297 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); in ar5416_init_from_rom()
298 reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize); in ar5416_init_from_rom()
308 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); in ar5416_init_from_rom()
[all …]
H A Dar9003.c564 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); in ar9003_rfsilent_init()
820 reg = RW(reg, AR_RXBP_THRESH_HP, 1); in ar9003_rx_enable()
821 reg = RW(reg, AR_RXBP_THRESH_LP, 1); in ar9003_rx_enable()
1864 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); in ar9003_set_delta_slope()
1865 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); in ar9003_set_delta_slope()
1874 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); in ar9003_set_delta_slope()
1875 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); in ar9003_set_delta_slope()
1966 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); in ar9003_write_noisefloor()
1970 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); in ar9003_write_noisefloor()
2125 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); in ar9003_do_calib()
[all …]
H A Dar5008.c462 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); in ar5008_rfsilent_init()
1926 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); in ar5008_set_delta_slope()
1927 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); in ar5008_set_delta_slope()
1936 reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp); in ar5008_set_delta_slope()
1937 reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man); in ar5008_set_delta_slope()
2032 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); in ar5008_write_noisefloor()
2036 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); in ar5008_write_noisefloor()
2150 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log); in ar5008_do_calib()
2237 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff); in ar5008_calib_iq()
2238 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff); in ar5008_calib_iq()
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/openbsd-src/sys/dev/microcode/aic7xxx/
H A Daic79xx.reg91 access_mode RW
105 access_mode RW
122 access_mode RW
248 access_mode RW
264 access_mode RW
273 access_mode RW
281 access_mode RW
317 access_mode RW
326 access_mode RW
336 access_mode RW
[all …]
H A Daic7xxx.reg60 access_mode RW
77 access_mode RW
93 access_mode RW
170 access_mode RW
186 access_mode RW
208 access_mode RW
213 access_mode RW
226 access_mode RW
232 access_mode RW
241 access_mode RW
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/openbsd-src/gnu/llvm/libcxx/lib/abi/
H A Dpowerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist331 …d': True, 'name': '_ZNSt3__112__rs_default4__c_E', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
580 {'import_export': 'EXP', 'is_defined': True, 'name': '_ZNSt3__13cinE', 'storage_mapping_class': 'RW…
648 …P', 'is_defined': True, 'name': '_ZNSt3__14cerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
649 …P', 'is_defined': True, 'name': '_ZNSt3__14clogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
650 …P', 'is_defined': True, 'name': '_ZNSt3__14coutE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
659 …P', 'is_defined': True, 'name': '_ZNSt3__14wcinE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
663 …_defined': True, 'name': '_ZNSt3__15ctypeIcE2idE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
669 …_defined': True, 'name': '_ZNSt3__15ctypeIwE2idE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
684 …', 'is_defined': True, 'name': '_ZNSt3__15wcerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
685 …', 'is_defined': True, 'name': '_ZNSt3__15wclogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
[all …]
H A Dpowerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist331 …d': True, 'name': '_ZNSt3__112__rs_default4__c_E', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
580 {'import_export': 'EXP', 'is_defined': True, 'name': '_ZNSt3__13cinE', 'storage_mapping_class': 'RW…
648 …P', 'is_defined': True, 'name': '_ZNSt3__14cerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
649 …P', 'is_defined': True, 'name': '_ZNSt3__14clogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
650 …P', 'is_defined': True, 'name': '_ZNSt3__14coutE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
659 …P', 'is_defined': True, 'name': '_ZNSt3__14wcinE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
663 …_defined': True, 'name': '_ZNSt3__15ctypeIcE2idE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
669 …_defined': True, 'name': '_ZNSt3__15ctypeIwE2idE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
684 …', 'is_defined': True, 'name': '_ZNSt3__15wcerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
685 …', 'is_defined': True, 'name': '_ZNSt3__15wclogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
[all …]
/openbsd-src/gnu/llvm/compiler-rt/lib/tsan/tests/rtl/
H A Dtsan_test_util_posix.cpp107 else if (type_ == RW) in Init()
130 else if (type_ == RW) in Destroy()
142 else if (type_ == RW) in Lock()
154 else if (type_ == RW) in TryLock()
167 else if (type_ == RW) in Unlock()
173 CHECK(type_ == RW); in ReadLock()
179 CHECK(type_ == RW); in TryReadLock()
185 CHECK(type_ == RW); in ReadUnlock()
H A Dtsan_mop.cpp68 UserMutex m(UserMutex::RW); in TEST_F()
87 UserMutex m(UserMutex::RW); in TEST_F()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask() local
101 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
102 : BT::BitMask(RW, 2*RW-1); in mask()
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
277 assert(RW <= RC.width()); in evaluate()
278 return eXTR(RC, 0, RW); in evaluate()
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate() argument
284 assert(RW <= W); in evaluate()
285 return eXTR(RC, W-RW, W); in evaluate()
345 uint16_t RW = W0; in evaluate() local
[all …]
/openbsd-src/usr.bin/uuencode/
H A Duuencode.c114 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) in main() macro
115 mode = RW & ~umask(RW); in main()
/openbsd-src/gnu/llvm/clang/utils/ABITest/
H A DEnumeration.py152 LW,RW = W//2, W - (W//2)
153 L,R = getNthPairBounded(N, H**LW, H**RW)
155 getNthNTuple(R,RW,H=H,useLeftToRight=useLeftToRight))
/openbsd-src/gnu/usr.bin/perl/cpan/Encode/t/
H A Dat-cn.t65 '!6RW>-!75ZR;XT',
78 '!6RW>-!75ZR;XT',
/openbsd-src/regress/lib/libcrypto/x509/bettertls/certificates/
H A D671.crt13 46KrreoF/RW+PYlIrlhnbm2G5+pf94Dj7lMtRlBLqqX08/MtYJJP+z7ASgur5ADO
H A D2556.crt17 YWyHBH8AAAEwDQYJKoZIhvcNAQELBQADggEBAH+cXvN/REbgfSvP+RW/HeuVeyeO
H A D2836.key16 RW/z+LBrCE8j1rzH8kwFMCoWiXUzHyTgp+YTI6sEhINt/pD97arPl4jeeu/Y2+O6
H A D1222.key8 ZmjBBnX89+RW+KjemkBn0UuSa5/DSeQZog2E1aQgluA/ltmlq2oP6WRhG0GNuqRb
H A D1301.key18 RW+NwkrptrddQB5Yk54STOzLKJKraSIsExFL1e0CgYBNUERXsG0AvyzZ2NfLi2df
H A D2812.key8 Fmj4DldUp0qT6f9zA5W+RW/uXnwOzAAYLKvy2vxSG0sJD2oLsntD+Nuy2QjQkb56
/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp609 for (Record *RW : RWs) { in collectSchedRW()
610 if (RW->isSubClassOf("SchedWrite")) in collectSchedRW()
611 scanSchedRW(RW, SWDefs, RWSet); in collectSchedRW()
613 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
614 scanSchedRW(RW, SRDefs, RWSet); in collectSchedRW()
689 CodeGenSchedRW &RW = getSchedRW(MatchDef); in collectSchedRW() local
690 if (RW.IsAlias) in collectSchedRW()
692 RW.Aliases.push_back(ADef); in collectSchedRW()
732 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; }); in getSchedRWIdx() argument
840 auto I = find_if(RWVec, [Seq](CodeGenSchedRW &RW) { in findRWForSequence() argument
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