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Searched refs:REV64 (Results 1 – 5 of 5) sorted by relevance

/openbsd-src/gnu/llvm/llvm/docs/
H A DBigEndianNEON.rst194 … REV64 v0.4s, v0.4s // There is no REV128 instruction, so it must be synthesizedcd
195 EXT v0.16b, v0.16b, v0.16b, #8 // with a REV64 then an EXT to swap the two 64-bit elements.
197 REV64 v0.2d, v0.2d
202 …`. For the example above, a ``REV128 4s`` + ``REV128 2d`` is actually a ``REV64 4s``, as shown in …
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h205 REV64, enumerator
H A DAArch64SchedCyclone.td504 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
H A DAArch64ISelLowering.cpp2387 MAKE_CASE(AArch64ISD::REV64) in getTargetNodeName()
8786 REVB = DAG.getNode(AArch64ISD::REV64, DL, VST, Op.getOperand(0)); in LowerBitreverse()
8793 REVB = DAG.getNode(AArch64ISD::REV64, DL, VST, Op.getOperand(0)); in LowerBitreverse()
11110 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
11528 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
11537 SDValue Rev = DAG.getNode(AArch64ISD::REV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
H A DAArch64InstrInfo.td662 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
4619 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;