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Searched refs:RCP (Results 1 – 10 of 10) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h420 RCP, enumerator
H A DAMDGPUCodeGenPrepare.cpp956 Value *RCP = Builder.CreateCall(RcpDecl, { FB }); in expandDivRem24Impl() local
957 Value *FQM = Builder.CreateFMul(FA, RCP); in expandDivRem24Impl()
H A DAMDGPUISelLowering.cpp575 case AMDGPUISD::RCP: in fnegFoldsIntoOp()
1739 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb)); in LowerDIVREM24()
1855 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64()
3981 case AMDGPUISD::RCP: in performFNegCombine()
4267 case AMDGPUISD::RCP: in PerformDAGCombine()
4443 NODE_NAME_CASE(RCP) in getTargetNodeName()
4582 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand); in getRecipEstimate()
4864 case AMDGPUISD::RCP: in isKnownNeverNaNForTargetNode()
H A DAMDGPUInstrInfo.td112 def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
H A DAMDGPULegalizerInfo.cpp3767 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy}, false) in legalizeFastUnsafeFDIV() local
3770 B.buildFMul(Res, LHS, RCP, Flags); in legalizeFastUnsafeFDIV()
3831 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) in legalizeFDIV16() local
3835 auto QUOT = B.buildFMul(S32, LHSExt, RCP, Flags); in legalizeFDIV16()
4051 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) in legalizeFDIVFastIntrin() local
4055 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags); in legalizeFDIVFastIntrin()
H A DSIISelLowering.cpp6888 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
8910 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8917 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS); in lowerFastUnsafeFDIV()
8923 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8943 SDValue R = DAG.getNode(AMDGPUISD::RCP, SL, VT, Y); in lowerFastUnsafeFDIV64()
9009 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1); in LowerFDIV16()
9045 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1); in lowerFDIV_FAST()
9090 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, in LowerFDIV32()
9197 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64()
10116 case AMDGPUISD::RCP: in isCanonicalized()
[all …]
H A DAMDGPUISelDAGToDAG.cpp178 case AMDGPUISD::RCP: in fp16SrcZerosHighBits()
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/config/
H A Dtc-arm.c9225 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
9226 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
9227 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
9228 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
9229 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
9230 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9231 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9284 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
9285 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
9286 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrSSE.td3061 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SchedWriteFRcp, HasAVX>,
/openbsd-src/gnu/usr.bin/gcc/gcc/
H A DChangeLog.1139 Thu May 13 01:49:55 1999 Graham Stott <GrahamS@RCP.co.uk>