Searched refs:RBGPR (Results 1 – 3 of 3) sorted by relevance
141 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo() local142 (void)RBGPR; in ARMRegisterBankInfo()143 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()146 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()148 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()152 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()154 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()156 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()158 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()[all …]
31 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo() local32 (void)RBGPR; in X86RegisterBankInfo()33 assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization."); in X86RegisterBankInfo()37 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()39 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in X86RegisterBankInfo()
55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() local56 (void)RBGPR; in AArch64RegisterBankInfo()57 assert(&AArch64::GPRRegBank == &RBGPR && in AArch64RegisterBankInfo()72 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()74 assert(RBGPR.getSize() == 128 && "GPRs should hold up to 128-bit"); in AArch64RegisterBankInfo()107 CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); in AArch64RegisterBankInfo()108 CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); in AArch64RegisterBankInfo()109 CHECK_PARTIALMAP(PMI_GPR128, 0, 128, RBGPR); in AArch64RegisterBankInfo()