| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 320 Register PtrReg = Store.getPointerReg(); in applySplitStoreZero128() local
322 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
327 B.buildStore(Zero, PtrReg, *LowMMO); in applySplitStoreZero128()
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| H A D | AArch64InstructionSelector.cpp | 2863 const Register PtrReg = LdSt.getPointerReg(); in select() local
2864 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2868 assert(MRI.getType(PtrReg).isPointer() && in select()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 425 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
426 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]); in lowerParameter()
445 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
555 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
556 lowerParameterPtr(PtrReg, B, ArgOffset); in lowerFormalArgumentsKernel()
558 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
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| H A D | AMDGPURegisterBankInfo.cpp | 1076 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1087 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1091 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1095 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
1112 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0); in applyMappingLoad()
3428 Register PtrReg) const { in getValueMappingForPtr()
3429 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
3437 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3448 Register PtrReg = MI.getOperand(1).getReg(); in getInstrMappingForLoad() local
3449 LLT PtrTy = MRI.getType(PtrReg); in getInstrMappingForLoad()
[all …]
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| H A D | AMDGPULegalizerInfo.cpp | 2604 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
2605 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
2610 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
2655 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2663 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2668 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2705 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
2709 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
2719 .addUse(PtrReg) in legalizeAtomicCmpXChg()
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| H A D | AMDGPUInstructionSelector.cpp | 3858 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
3865 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 727 Register PtrReg = LoadMI->getPointerReg(); in matchCombineLoadWithAndMask() local
759 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
767 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO); in matchCombineLoadWithAndMask()
2056 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2064 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2066 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2069 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2074 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2081 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2086 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
[all …]
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| H A D | LegalizerHelper.cpp | 1060 Register PtrReg = LoadMI.getPointerReg(); in narrowScalar() local
1067 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
1069 MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO); in narrowScalar()
2936 Register PtrReg = LoadMI.getPointerReg(); in lowerLoad() local
2966 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad()
2969 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad()
2974 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
3036 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
3040 PtrReg, *LargeMMO); in lowerLoad()
3045 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); in lowerLoad()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11769 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
11831 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
11836 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
11857 .addReg(PtrReg); in EmitPartwordAtomicBinary()
11900 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12761 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
12830 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
12835 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
12867 .addReg(PtrReg); in EmitInstrWithCustomInserter()
12891 .addReg(PtrReg); in EmitInstrWithCustomInserter()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4872 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
4873 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()
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