Home
last modified time | relevance | path

Searched refs:PredReg (Results 1 – 25 of 27) sorted by relevance

12

/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp175 ARMCC::CondCodes Pred, unsigned PredReg);
179 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
490 unsigned PredReg) { in UpdateBaseRegUses() argument
559 .addReg(PredReg); in UpdateBaseRegUses()
580 .addReg(PredReg); in UpdateBaseRegUses()
630 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti() argument
750 .add(predOps(Pred, PredReg)); in CreateLoadStoreMulti()
761 .add(predOps(Pred, PredReg)); in CreateLoadStoreMulti()
767 .add(predOps(Pred, PredReg)); in CreateLoadStoreMulti()
[all …]
H A DThumb2InstrInfo.h78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
84 Register &PredReg);
86 Register PredReg; in getVPTInstrPredicate() local
87 return getVPTInstrPredicate(MI, PredReg); in getVPTInstrPredicate()
H A DThumb2InstrInfo.cpp73 Register PredReg; in ReplaceTailWithBranchTo() local
74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
121 Register PredReg; in isLegalToSplitMBBAt() local
122 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
295 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate() argument
301 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
318 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
325 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
334 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
346 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
[all …]
H A DMVEVPTBlockPass.cpp106 Register PredReg; in StepOverPredicatedInstrs() local
116 NextPred = getVPTInstrPredicate(*Iter, PredReg); in StepOverPredicatedInstrs()
251 Register PredReg; in InsertVPTBlocks() local
254 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg); in InsertVPTBlocks()
H A DThumb2SizeReduction.cpp469 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
482 .addReg(PredReg) in ReduceLoadStore()
687 Register PredReg; in ReduceSpecial() local
688 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
729 Register PredReg; in ReduceSpecial() local
731 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) in ReduceSpecial()
800 Register PredReg; in ReduceTo2Addr() local
801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
892 Register PredReg; in ReduceToNarrow() local
893 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
77 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
113 PredReg, MIFlags); in emitLoadConstPool()
116 PredReg, MIFlags); in emitLoadConstPool()
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
295 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
307 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
H A DThumbRegisterInfo.h43 Register PredReg = Register(),
H A DThumb2ITBlockPass.cpp202 Register PredReg; in InsertITInstructions() local
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
H A DARMBaseInstrInfo.h543 unsigned PredReg = 0) {
545 MachineOperand::CreateReg(PredReg, false)}};
783 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
799 ARMCC::CondCodes Pred, Register PredReg,
806 ARMCC::CondCodes Pred, Register PredReg,
H A DARMBaseRegisterInfo.cpp499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
511 .add(predOps(Pred, PredReg)) in emitLoadConstPool()
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
865 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
869 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
H A DARMConstantIslandPass.cpp1456 Register PredReg; in createNewWater() local
1459 getITInstrPredicate(*I, PredReg) != ARMCC::AL; in createNewWater()
1502 Register PredReg; in createNewWater() local
1503 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in createNewWater()
1526 Register PredReg; in createNewWater() local
1527 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL); in createNewWater()
1929 Register PredReg; in optimizeThumb2Branches() local
1931 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); in optimizeThumb2Branches()
H A DARMBaseRegisterInfo.h217 Register PredReg = Register(),
H A DARMFrameLowering.cpp539 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate() argument
542 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
545 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
553 unsigned PredReg = 0) { in emitSPUpdate() argument
555 MIFlags, Pred, PredReg); in emitSPUpdate()
2845 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr() local
2864 Pred, PredReg); in eliminateCallFramePseudoInstr()
2868 Pred, PredReg); in eliminateCallFramePseudoInstr()
2875 MachineInstr::NoFlags, Pred, PredReg); in eliminateCallFramePseudoInstr()
H A DARMISelDAGToDAG.cpp1753 SDValue PredReg; in tryMVEIndexedLoad() local
1771 PredReg = CurDAG->getRegister(0, MVT::i32); in tryMVEIndexedLoad()
1787 PredReg = LD->getMask(); in tryMVEIndexedLoad()
1834 PredReg, in tryMVEIndexedLoad()
2924 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
2926 Ops.push_back(PredReg); in SelectCDE_CXxD()
4281 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4282 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select()
4293 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4294 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select()
[all …]
H A DARMBaseInstrInfo.cpp2247 Register &PredReg) { in getInstrPredicate() argument
2250 PredReg = 0; in getInstrPredicate()
2254 PredReg = MI.getOperand(PIdx+1).getReg(); in getInstrPredicate()
2277 Register PredReg; in commuteInstructionImpl() local
2278 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2280 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2485 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate() argument
2491 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
2515 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
5616 Register PredReg; in findCMPToFoldIntoCBZ() local
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp177 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
187 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
189 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
191 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
193 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
H A DHexagonMCChecker.cpp68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg() argument
73 PredReg = R; in initReg()
78 NewPreds.insert(PredReg); in initReg()
94 unsigned PredReg = Hexagon::NoRegister; in init() local
100 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue); in init()
102 initReg(MCI, ImpUse, PredReg, isTrue); in init()
131 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
186 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
H A DHexagonMCChecker.h81 void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
473 PredReg = MCI.getOperand(1).getReg(); // P0 in getDuplexCandidateGroup()
475 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) { in getDuplexCandidateGroup()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp121 bool isScalarPred(RegisterSubReg PredReg);
321 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred() argument
323 WorkQ.push(PredReg); in isScalarPred()
H A DHexagonInstrInfo.h433 bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
467 bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
H A DHexagonInstrInfo.cpp1699 Register PredReg; in PredicateInstruction() local
1701 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); in PredicateInstruction()
1704 T.addReg(PredReg, PredRegFlags); in PredicateInstruction()
1718 MRI.clearKillFlags(PredReg); in PredicateInstruction()
3198 Register PredReg) const { in predCanBeUsedAsDotNew()
3201 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) in predCanBeUsedAsDotNew()
3203 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) in predCanBeUsedAsDotNew()
4520 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg() argument
4528 PredReg = Cond[1].getReg(); in getPredReg()
H A DHexagonHardwareLoops.cpp651 Register PredReg; in getLoopTripCount() local
653 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) in getLoopTripCount()
655 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h372 unsigned PredReg,

12